mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 11:55:49 +07:00
2d2474a194
Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
1290 lines
33 KiB
Plaintext
1290 lines
33 KiB
Plaintext
#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra210-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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/ {
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compatible = "nvidia,tegra210";
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interrupt-parent = <&lic>;
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#address-cells = <2>;
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#size-cells = <2>;
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host1x@50000000 {
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compatible = "nvidia,tegra210-host1x", "simple-bus";
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reg = <0x0 0x50000000 0x0 0x00034000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
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dpaux1: dpaux@54040000 {
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compatible = "nvidia,tegra210-dpaux";
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reg = <0x0 0x54040000 0x0 0x00040000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
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<&tegra_car TEGRA210_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 207>;
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reset-names = "dpaux";
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power-domains = <&pd_sor>;
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status = "disabled";
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state_dpaux1_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux1_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux1_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vi@54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x0 0x54080000 0x0 0x00040000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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tsec@54100000 {
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compatible = "nvidia,tegra210-tsec";
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reg = <0x0 0x54100000 0x0 0x00040000>;
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};
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dc@54200000 {
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compatible = "nvidia,tegra210-dc";
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reg = <0x0 0x54200000 0x0 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DISP1>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DC>;
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nvidia,head = <0>;
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};
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dc@54240000 {
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compatible = "nvidia,tegra210-dc";
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reg = <0x0 0x54240000 0x0 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DISP2>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DCB>;
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nvidia,head = <1>;
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};
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dsi@54300000 {
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compatible = "nvidia,tegra210-dsi";
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reg = <0x0 0x54300000 0x0 0x00040000>;
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clocks = <&tegra_car TEGRA210_CLK_DSIA>,
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<&tegra_car TEGRA210_CLK_DSIALP>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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power-domains = <&pd_sor>;
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nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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vic@54340000 {
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compatible = "nvidia,tegra210-vic";
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reg = <0x0 0x54340000 0x0 0x00040000>;
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status = "disabled";
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};
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nvjpg@54380000 {
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compatible = "nvidia,tegra210-nvjpg";
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reg = <0x0 0x54380000 0x0 0x00040000>;
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status = "disabled";
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};
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dsi@54400000 {
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compatible = "nvidia,tegra210-dsi";
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reg = <0x0 0x54400000 0x0 0x00040000>;
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clocks = <&tegra_car TEGRA210_CLK_DSIB>,
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<&tegra_car TEGRA210_CLK_DSIBLP>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 82>;
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reset-names = "dsi";
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power-domains = <&pd_sor>;
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nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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nvdec@54480000 {
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compatible = "nvidia,tegra210-nvdec";
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reg = <0x0 0x54480000 0x0 0x00040000>;
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status = "disabled";
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};
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nvenc@544c0000 {
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compatible = "nvidia,tegra210-nvenc";
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reg = <0x0 0x544c0000 0x0 0x00040000>;
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status = "disabled";
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};
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tsec@54500000 {
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compatible = "nvidia,tegra210-tsec";
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reg = <0x0 0x54500000 0x0 0x00040000>;
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status = "disabled";
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};
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sor@54540000 {
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compatible = "nvidia,tegra210-sor";
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reg = <0x0 0x54540000 0x0 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SOR0>,
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_DP>,
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<&tegra_car TEGRA210_CLK_SOR_SAFE>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 182>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux_aux>;
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pinctrl-1 = <&state_dpaux_i2c>;
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pinctrl-2 = <&state_dpaux_off>;
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pinctrl-names = "aux", "i2c", "off";
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power-domains = <&pd_sor>;
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status = "disabled";
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};
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sor@54580000 {
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compatible = "nvidia,tegra210-sor1";
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reg = <0x0 0x54580000 0x0 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SOR1>,
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<&tegra_car TEGRA210_CLK_SOR1_SRC>,
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<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_DP>,
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<&tegra_car TEGRA210_CLK_SOR_SAFE>;
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clock-names = "sor", "source", "parent", "dp", "safe";
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resets = <&tegra_car 183>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux1_aux>;
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pinctrl-1 = <&state_dpaux1_i2c>;
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pinctrl-2 = <&state_dpaux1_off>;
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pinctrl-names = "aux", "i2c", "off";
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power-domains = <&pd_sor>;
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status = "disabled";
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};
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dpaux: dpaux@545c0000 {
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compatible = "nvidia,tegra124-dpaux";
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reg = <0x0 0x545c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
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<&tegra_car TEGRA210_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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power-domains = <&pd_sor>;
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status = "disabled";
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state_dpaux_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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isp@54600000 {
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compatible = "nvidia,tegra210-isp";
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reg = <0x0 0x54600000 0x0 0x00040000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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isp@54680000 {
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compatible = "nvidia,tegra210-isp";
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reg = <0x0 0x54680000 0x0 0x00040000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c@546c0000 {
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compatible = "nvidia,tegra210-i2c-vi";
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reg = <0x0 0x546c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@50041000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x50041000 0x0 0x1000>,
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<0x0 0x50042000 0x0 0x2000>,
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<0x0 0x50044000 0x0 0x2000>,
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<0x0 0x50046000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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gpu@57000000 {
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compatible = "nvidia,gm20b";
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reg = <0x0 0x57000000 0x0 0x01000000>,
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<0x0 0x58000000 0x0 0x01000000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&tegra_car TEGRA210_CLK_GPU>,
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<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
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<&tegra_car TEGRA210_CLK_PLL_G_REF>;
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clock-names = "gpu", "pwr", "ref";
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resets = <&tegra_car 184>;
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reset-names = "gpu";
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iommus = <&mc TEGRA_SWGROUP_GPU>;
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status = "disabled";
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};
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lic: interrupt-controller@60004000 {
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compatible = "nvidia,tegra210-ictlr";
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reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
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<0x0 0x60004100 0x0 0x40>, /* secondary controller */
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<0x0 0x60004200 0x0 0x40>, /* tertiary controller */
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<0x0 0x60004300 0x0 0x40>, /* quaternary controller */
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<0x0 0x60004400 0x0 0x40>, /* quinary controller */
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<0x0 0x60004500 0x0 0x40>; /* senary controller */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
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reg = <0x0 0x60005000 0x0 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TIMER>;
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clock-names = "timer";
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra210-car";
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reg = <0x0 0x60006000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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flow-controller@60007000 {
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compatible = "nvidia,tegra210-flowctrl";
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reg = <0x0 0x60007000 0x0 0x1000>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
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reg = <0x0 0x6000d000 0x0 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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apbdma: dma@60020000 {
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compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x0 0x60020000 0x0 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
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clock-names = "dma";
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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apbmisc@70000800 {
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compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
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reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
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<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
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};
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pinmux: pinmux@700008d4 {
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compatible = "nvidia,tegra210-pinmux";
|
|
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
|
|
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
|
|
};
|
|
|
|
/*
|
|
* There are two serial driver i.e. 8250 based simple serial
|
|
* driver and APB DMA based serial driver for higher baudrate
|
|
* and performance. To enable the 8250 based driver, the compatible
|
|
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
|
|
* the APB DMA based serial driver, the compatible is
|
|
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
|
*/
|
|
uarta: serial@70006000 {
|
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0 0x70006000 0x0 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
|
|
clock-names = "serial";
|
|
resets = <&tegra_car 6>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 8>, <&apbdma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartb: serial@70006040 {
|
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0 0x70006040 0x0 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
|
|
clock-names = "serial";
|
|
resets = <&tegra_car 7>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 9>, <&apbdma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@70006200 {
|
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0 0x70006200 0x0 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
|
|
clock-names = "serial";
|
|
resets = <&tegra_car 55>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 10>, <&apbdma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartd: serial@70006300 {
|
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0 0x70006300 0x0 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
|
|
clock-names = "serial";
|
|
resets = <&tegra_car 65>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 19>, <&apbdma 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@7000a000 {
|
|
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
|
|
reg = <0x0 0x7000a000 0x0 0x100>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&tegra_car TEGRA210_CLK_PWM>;
|
|
clock-names = "pwm";
|
|
resets = <&tegra_car 17>;
|
|
reset-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000c000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C1>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 12>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 21>, <&apbdma 21>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000c400 0x0 0x100>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C2>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 54>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 22>, <&apbdma 22>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000c500 0x0 0x100>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C3>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 67>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 23>, <&apbdma 23>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c700 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000c700 0x0 0x100>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C4>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 103>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 26>, <&apbdma 26>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-0 = <&state_dpaux1_i2c>;
|
|
pinctrl-1 = <&state_dpaux1_off>;
|
|
pinctrl-names = "default", "idle";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000d000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C5>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 47>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 24>, <&apbdma 24>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d100 {
|
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
|
|
reg = <0x0 0x7000d100 0x0 0x100>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_I2C6>;
|
|
clock-names = "div-clk";
|
|
resets = <&tegra_car 166>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 30>, <&apbdma 30>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-0 = <&state_dpaux_i2c>;
|
|
pinctrl-1 = <&state_dpaux_off>;
|
|
pinctrl-names = "default", "idle";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d400 {
|
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
|
reg = <0x0 0x7000d400 0x0 0x200>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 41>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 15>, <&apbdma 15>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
|
reg = <0x0 0x7000d600 0x0 0x200>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 44>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 16>, <&apbdma 16>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
|
reg = <0x0 0x7000d800 0x0 0x200>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 46>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 17>, <&apbdma 17>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
|
|
reg = <0x0 0x7000da00 0x0 0x200>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 68>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 18>, <&apbdma 18>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@7000e000 {
|
|
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
|
|
reg = <0x0 0x7000e000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_RTC>;
|
|
clock-names = "rtc";
|
|
};
|
|
|
|
pmc: pmc@7000e400 {
|
|
compatible = "nvidia,tegra210-pmc";
|
|
reg = <0x0 0x7000e400 0x0 0x400>;
|
|
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
|
|
powergates {
|
|
pd_audio: aud {
|
|
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
|
<&tegra_car TEGRA210_CLK_APB2APE>;
|
|
resets = <&tegra_car 198>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_sor: sor {
|
|
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
|
|
<&tegra_car TEGRA210_CLK_SOR1>,
|
|
<&tegra_car TEGRA210_CLK_CSI>,
|
|
<&tegra_car TEGRA210_CLK_DSIA>,
|
|
<&tegra_car TEGRA210_CLK_DSIB>,
|
|
<&tegra_car TEGRA210_CLK_DPAUX>,
|
|
<&tegra_car TEGRA210_CLK_DPAUX1>,
|
|
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
|
|
resets = <&tegra_car TEGRA210_CLK_SOR0>,
|
|
<&tegra_car TEGRA210_CLK_SOR1>,
|
|
<&tegra_car TEGRA210_CLK_CSI>,
|
|
<&tegra_car TEGRA210_CLK_DSIA>,
|
|
<&tegra_car TEGRA210_CLK_DSIB>,
|
|
<&tegra_car TEGRA210_CLK_DPAUX>,
|
|
<&tegra_car TEGRA210_CLK_DPAUX1>,
|
|
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_xusbss: xusba {
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
|
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_xusbdev: xusbb {
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
|
|
resets = <&tegra_car 95>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_xusbhost: xusbc {
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
|
|
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
fuse@7000f800 {
|
|
compatible = "nvidia,tegra210-efuse";
|
|
reg = <0x0 0x7000f800 0x0 0x400>;
|
|
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
|
|
clock-names = "fuse";
|
|
resets = <&tegra_car 39>;
|
|
reset-names = "fuse";
|
|
};
|
|
|
|
mc: memory-controller@70019000 {
|
|
compatible = "nvidia,tegra210-mc";
|
|
reg = <0x0 0x70019000 0x0 0x1000>;
|
|
clocks = <&tegra_car TEGRA210_CLK_MC>;
|
|
clock-names = "mc";
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
hda@70030000 {
|
|
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
|
|
reg = <0x0 0x70030000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_HDA>,
|
|
<&tegra_car TEGRA210_CLK_HDA2HDMI>,
|
|
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
|
|
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
resets = <&tegra_car 125>, /* hda */
|
|
<&tegra_car 128>, /* hda2hdmi */
|
|
<&tegra_car 111>; /* hda2codec_2x */
|
|
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@70090000 {
|
|
compatible = "nvidia,tegra210-xusb";
|
|
reg = <0x0 0x70090000 0x0 0x8000>,
|
|
<0x0 0x70098000 0x0 0x1000>,
|
|
<0x0 0x70099000 0x0 0x1000>;
|
|
reg-names = "hcd", "fpci", "ipfs";
|
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_SS>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
|
|
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
|
|
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
|
|
<&tegra_car TEGRA210_CLK_CLK_M>,
|
|
<&tegra_car TEGRA210_CLK_PLL_E>;
|
|
clock-names = "xusb_host", "xusb_host_src",
|
|
"xusb_falcon_src", "xusb_ss",
|
|
"xusb_ss_div2", "xusb_ss_src",
|
|
"xusb_hs_src", "xusb_fs_src",
|
|
"pll_u_480m", "clk_m", "pll_e";
|
|
resets = <&tegra_car 89>, <&tegra_car 156>,
|
|
<&tegra_car 143>;
|
|
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
|
|
|
nvidia,xusb-padctl = <&padctl>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
padctl: padctl@7009f000 {
|
|
compatible = "nvidia,tegra210-xusb-padctl";
|
|
reg = <0x0 0x7009f000 0x0 0x1000>;
|
|
resets = <&tegra_car 142>;
|
|
reset-names = "padctl";
|
|
|
|
status = "disabled";
|
|
|
|
pads {
|
|
usb2 {
|
|
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
|
|
clock-names = "trk";
|
|
status = "disabled";
|
|
|
|
lanes {
|
|
usb2-0 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb2-1 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb2-2 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb2-3 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hsic {
|
|
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
|
|
clock-names = "trk";
|
|
status = "disabled";
|
|
|
|
lanes {
|
|
hsic-0 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
hsic-1 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
|
|
clock-names = "pll";
|
|
resets = <&tegra_car 205>;
|
|
reset-names = "phy";
|
|
status = "disabled";
|
|
|
|
lanes {
|
|
pcie-0 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-1 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-2 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-3 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-4 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-5 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie-6 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sata {
|
|
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
|
|
clock-names = "pll";
|
|
resets = <&tegra_car 204>;
|
|
reset-names = "phy";
|
|
status = "disabled";
|
|
|
|
lanes {
|
|
sata-0 {
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
usb2-0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2-1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2-2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2-3 {
|
|
status = "disabled";
|
|
};
|
|
|
|
hsic-0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3-0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3-1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3-2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3-3 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdhci@700b0000 {
|
|
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
|
clock-names = "sdhci";
|
|
resets = <&tegra_car 14>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@700b0200 {
|
|
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0200 0x0 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
|
|
clock-names = "sdhci";
|
|
resets = <&tegra_car 9>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@700b0400 {
|
|
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0400 0x0 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
|
|
clock-names = "sdhci";
|
|
resets = <&tegra_car 69>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@700b0600 {
|
|
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
|
reg = <0x0 0x700b0600 0x0 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
|
|
clock-names = "sdhci";
|
|
resets = <&tegra_car 15>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi: mipi@700e3000 {
|
|
compatible = "nvidia,tegra210-mipi";
|
|
reg = <0x0 0x700e3000 0x0 0x100>;
|
|
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
|
|
clock-names = "mipi-cal";
|
|
power-domains = <&pd_sor>;
|
|
#nvidia,mipi-calibrate-cells = <1>;
|
|
};
|
|
|
|
aconnect@702c0000 {
|
|
compatible = "nvidia,tegra210-aconnect";
|
|
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
|
<&tegra_car TEGRA210_CLK_APB2APE>;
|
|
clock-names = "ape", "apb2ape";
|
|
power-domains = <&pd_audio>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
|
|
status = "disabled";
|
|
|
|
adma: dma@702e2000 {
|
|
compatible = "nvidia,tegra210-adma";
|
|
reg = <0x702e2000 0x2000>;
|
|
interrupt-parent = <&agic>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
|
|
clock-names = "d_audio";
|
|
status = "disabled";
|
|
};
|
|
|
|
agic: agic@702f9000 {
|
|
compatible = "nvidia,tegra210-agic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x702f9000 0x2000>,
|
|
<0x702fa000 0x2000>;
|
|
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&tegra_car TEGRA210_CLK_APE>;
|
|
clock-names = "clk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spi@70410000 {
|
|
compatible = "nvidia,tegra210-qspi";
|
|
reg = <0x0 0x70410000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA210_CLK_QSPI>;
|
|
clock-names = "qspi";
|
|
resets = <&tegra_car 211>;
|
|
reset-names = "qspi";
|
|
dmas = <&apbdma 5>, <&apbdma 5>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x0 0x7d000000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA210_CLK_USBD>;
|
|
clock-names = "usb";
|
|
resets = <&tegra_car 22>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@7d000000 {
|
|
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
|
reg = <0x0 0x7d000000 0x0 0x4000>,
|
|
<0x0 0x7d000000 0x0 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA210_CLK_USBD>,
|
|
<&tegra_car TEGRA210_CLK_PLL_U>,
|
|
<&tegra_car TEGRA210_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 22>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
nvidia,has-utmi-pad-registers;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d004000 {
|
|
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x0 0x7d004000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA210_CLK_USB2>;
|
|
clock-names = "usb";
|
|
resets = <&tegra_car 58>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy2: usb-phy@7d004000 {
|
|
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
|
|
reg = <0x0 0x7d004000 0x0 0x4000>,
|
|
<0x0 0x7d000000 0x0 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA210_CLK_USB2>,
|
|
<&tegra_car TEGRA210_CLK_PLL_U>,
|
|
<&tegra_car TEGRA210_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 58>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
soctherm: thermal-sensor@700e2000 {
|
|
compatible = "nvidia,tegra210-soctherm";
|
|
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
|
|
0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
|
|
reg-names = "soctherm-reg", "car-reg";
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
|
|
<&tegra_car TEGRA210_CLK_SOC_THERM>;
|
|
clock-names = "tsensor", "soctherm";
|
|
resets = <&tegra_car 78>;
|
|
reset-names = "soctherm";
|
|
#thermal-sensor-cells = <1>;
|
|
|
|
throttle-cfgs {
|
|
throttle_heavy: heavy {
|
|
nvidia,priority = <100>;
|
|
nvidia,cpu-throt-percent = <85>;
|
|
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors =
|
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
|
|
|
|
trips {
|
|
cpu-shutdown-trip {
|
|
temperature = <102500>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
|
|
cpu_throttle_trip: throttle-trip {
|
|
temperature = <98500>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_throttle_trip>;
|
|
cooling-device = <&throttle_heavy 1 1>;
|
|
};
|
|
};
|
|
};
|
|
mem {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors =
|
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
|
|
|
|
trips {
|
|
mem-shutdown-trip {
|
|
temperature = <103000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
/*
|
|
* There are currently no cooling maps,
|
|
* because there are no cooling devices.
|
|
*/
|
|
};
|
|
};
|
|
gpu {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors =
|
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
|
|
|
|
trips {
|
|
gpu-shutdown-trip {
|
|
temperature = <103000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
|
|
gpu_throttle_trip: throttle-trip {
|
|
temperature = <100000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu_throttle_trip>;
|
|
cooling-device = <&throttle_heavy 1 1>;
|
|
};
|
|
};
|
|
};
|
|
pllx {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors =
|
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
|
|
|
|
trips {
|
|
pllx-shutdown-trip {
|
|
temperature = <103000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
/*
|
|
* There are currently no cooling maps,
|
|
* because there are no cooling devices.
|
|
*/
|
|
};
|
|
};
|
|
};
|
|
};
|