AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-26 00:05:35 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
9350852093
linux_dsm_epyc7002/arch/arm64/boot/dts/nvidia/tegra210.dtsi

1290 lines
33 KiB
Plaintext
Raw Normal View History

arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
#include <dt-bindings/thermal/tegra124-soctherm.h>
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
/ {
compatible = "nvidia,tegra210";
interrupt-parent = <&lic>;
#address-cells = <2>;
#size-cells = <2>;
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
host1x@50000000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-host1x", "simple-bus";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dpaux1: dpaux@54040000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x54040000 0x0 0x00040000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 207>;
reset-names = "dpaux";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
state_dpaux1_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux1_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux1_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
vi@54080000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-vi";
reg = <0x0 0x54080000 0x0 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
tsec@54100000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54100000 0x0 0x00040000>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dc@54200000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DISP1>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dc@54240000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DISP2>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dsi@54300000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIALP>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
vic@54340000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-vic";
reg = <0x0 0x54340000 0x0 0x00040000>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
nvjpg@54380000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-nvjpg";
reg = <0x0 0x54380000 0x0 0x00040000>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dsi@54400000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54400000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DSIBLP>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 82>;
reset-names = "dsi";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
nvdec@54480000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-nvdec";
reg = <0x0 0x54480000 0x0 0x00040000>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
nvenc@544c0000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-nvenc";
reg = <0x0 0x544c0000 0x0 0x00040000>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
tsec@54500000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54500000 0x0 0x00040000>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sor@54540000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
pinctrl-0 = <&state_dpaux_aux>;
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sor@54580000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sor1";
reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR1>,
arm64: tegra: Add sor1_src clock The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-09 22:50:57 +07:00
<&tegra_car TEGRA210_CLK_SOR1_SRC>,
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
arm64: tegra: Add sor1_src clock The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-09 22:50:57 +07:00
clock-names = "sor", "source", "parent", "dp", "safe";
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
resets = <&tegra_car 183>;
reset-names = "sor";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
pinctrl-0 = <&state_dpaux1_aux>;
pinctrl-1 = <&state_dpaux1_i2c>;
pinctrl-2 = <&state_dpaux1_off>;
pinctrl-names = "aux", "i2c", "off";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
dpaux: dpaux@545c0000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra124-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 181>;
reset-names = "dpaux";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
isp@54600000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
isp@54680000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@546c0000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c-vi";
reg = <0x0 0x546c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
gic: interrupt-controller@50041000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x50041000 0x0 0x1000>,
<0x0 0x50042000 0x0 0x2000>,
<0x0 0x50044000 0x0 0x2000>,
<0x0 0x50046000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
gpu@57000000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,gm20b";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&tegra_car TEGRA210_CLK_GPU>,
arm64: tegra: Add reference clock to GM20B on Tegra210 This clock is required for the GPU to operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-28 16:23:03 +07:00
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
clock-names = "gpu", "pwr", "ref";
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
resets = <&tegra_car 184>;
reset-names = "gpu";
arm64: tegra: Add IOMMU node to GM20B on Tegra210 The operating system driver can take advantage of the IOMMU to remove the need for physically contiguous memory buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-28 16:23:04 +07:00
iommus = <&mc TEGRA_SWGROUP_GPU>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
lic: interrupt-controller@60004000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-ictlr";
reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
<0x0 0x60004100 0x0 0x40>, /* secondary controller */
<0x0 0x60004200 0x0 0x40>, /* tertiary controller */
<0x0 0x60004300 0x0 0x40>, /* quaternary controller */
<0x0 0x60004400 0x0 0x40>, /* quinary controller */
<0x0 0x60004500 0x0 0x40>; /* senary controller */
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
timer@60005000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TIMER>;
clock-names = "timer";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
tegra_car: clock@60006000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
flow-controller@60007000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
gpio: gpio@6000d000 {
arm64: tegra: Simplify Tegra210 GPIO compatible value The compatible value need only include an entry for the specific HW generation, plus the oldest HW version that introduced changes it is backwards-compatible with; intermediate versions aren't necessary. Since Tegra124 GPIO is backwards-compatible with Tegra30 GPIO, there's no need to include the Tegra124 value in the Tegra210 DTS. This makes the kernel DT better match the copy of the DT files included in U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-16 00:31:32 +07:00
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
apbdma: dma@60020000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
reg = <0x0 0x60020000 0x0 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
clock-names = "dma";
resets = <&tegra_car 34>;
reset-names = "dma";
#dma-cells = <1>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
apbmisc@70000800 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
pinmux: pinmux@700008d4 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
};
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
arm64: Fix misspellings in comments. Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 00:52:41 +07:00
* and performance. To enable the 8250 based driver, the compatible
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
arm64: tegra: Fix copy/paste typo in several DTS includes The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-27 21:02:20 +07:00
* the APB DMA based serial driver, the compatible is
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
uarta: serial@70006000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
clock-names = "serial";
resets = <&tegra_car 6>;
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
uartb: serial@70006040 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
clock-names = "serial";
resets = <&tegra_car 7>;
reset-names = "serial";
dmas = <&apbdma 9>, <&apbdma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
uartc: serial@70006200 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
clock-names = "serial";
resets = <&tegra_car 55>;
reset-names = "serial";
dmas = <&apbdma 10>, <&apbdma 10>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
uartd: serial@70006300 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
clock-names = "serial";
resets = <&tegra_car 65>;
reset-names = "serial";
dmas = <&apbdma 19>, <&apbdma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
pwm: pwm@7000a000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car TEGRA210_CLK_PWM>;
clock-names = "pwm";
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000c000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C1>;
clock-names = "div-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000c400 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C2>;
clock-names = "div-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
dmas = <&apbdma 22>, <&apbdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000c500 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C3>;
clock-names = "div-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
dmas = <&apbdma 23>, <&apbdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000c700 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C4>;
clock-names = "div-clk";
resets = <&tegra_car 103>;
reset-names = "i2c";
dmas = <&apbdma 26>, <&apbdma 26>;
dma-names = "rx", "tx";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000d000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "div-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
dmas = <&apbdma 24>, <&apbdma 24>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
i2c@7000d100 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_I2C6>;
clock-names = "div-clk";
resets = <&tegra_car 166>;
reset-names = "i2c";
dmas = <&apbdma 30>, <&apbdma 30>;
dma-names = "rx", "tx";
arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 16:17:57 +07:00
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
pinctrl-names = "default", "idle";
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
spi@7000d400 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
clock-names = "spi";
resets = <&tegra_car 41>;
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
spi@7000d600 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
spi@7000d800 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
clock-names = "spi";
resets = <&tegra_car 46>;
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
spi@7000da00 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
clock-names = "spi";
resets = <&tegra_car 68>;
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
rtc@7000e000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_RTC>;
clock-names = "rtc";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
pmc: pmc@7000e400 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
arm64: tegra: Add audio powergate node for Tegra210 Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17 19:40:33 +07:00
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
#power-domain-cells = <0>;
};
arm64: tegra: Add XUSB powergates on Tegra210 The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-30 17:56:27 +07:00
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
pd_sor: sor {
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
resets = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
#power-domain-cells = <0>;
};
arm64: tegra: Add XUSB powergates on Tegra210 The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-30 17:56:27 +07:00
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
#power-domain-cells = <0>;
};
pd_xusbdev: xusbb {
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
resets = <&tegra_car 95>;
#power-domain-cells = <0>;
};
pd_xusbhost: xusbc {
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
#power-domain-cells = <0>;
};
arm64: tegra: Add audio powergate node for Tegra210 Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17 19:40:33 +07:00
};
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
fuse@7000f800 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-efuse";
reg = <0x0 0x7000f800 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
mc: memory-controller@70019000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA210_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
hda@70030000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_HDA>,
<&tegra_car TEGRA210_CLK_HDA2HDMI>,
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */
<&tegra_car 128>, /* hda2hdmi */
<&tegra_car 111>; /* hda2codec_2x */
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
status = "disabled";
};
arm64: tegra: Add Tegra210 XUSB controller Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-12 17:28:36 +07:00
usb@70090000 {
compatible = "nvidia,tegra210-xusb";
reg = <0x0 0x70090000 0x0 0x8000>,
<0x0 0x70098000 0x0 0x1000>,
<0x0 0x70099000 0x0 0x1000>;
reg-names = "hcd", "fpci", "ipfs";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-29 18:07:33 +07:00
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
arm64: tegra: Add Tegra210 XUSB controller Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-12 17:28:36 +07:00
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
<&tegra_car TEGRA210_CLK_CLK_M>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
<&tegra_car 143>;
reset-names = "xusb_host", "xusb_ss", "xusb_src";
nvidia,xusb-padctl = <&padctl>;
status = "disabled";
};
arm64: tegra: Add Tegra210 XUSB pad controller Add a device tree node for the XUSB pad controller found on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-12 17:28:35 +07:00
padctl: padctl@7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
status = "disabled";
pads {
usb2 {
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
usb2-0 {
status = "disabled";
#phy-cells = <0>;
};
usb2-1 {
status = "disabled";
#phy-cells = <0>;
};
usb2-2 {
status = "disabled";
#phy-cells = <0>;
};
usb2-3 {
status = "disabled";
#phy-cells = <0>;
};
};
};
hsic {
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
hsic-0 {
status = "disabled";
#phy-cells = <0>;
};
hsic-1 {
status = "disabled";
#phy-cells = <0>;
};
};
};
pcie {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 205>;
reset-names = "phy";
status = "disabled";
lanes {
pcie-0 {
status = "disabled";
#phy-cells = <0>;
};
pcie-1 {
status = "disabled";
#phy-cells = <0>;
};
pcie-2 {
status = "disabled";
#phy-cells = <0>;
};
pcie-3 {
status = "disabled";
#phy-cells = <0>;
};
pcie-4 {
status = "disabled";
#phy-cells = <0>;
};
pcie-5 {
status = "disabled";
#phy-cells = <0>;
};
pcie-6 {
status = "disabled";
#phy-cells = <0>;
};
};
};
sata {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 204>;
reset-names = "phy";
status = "disabled";
lanes {
sata-0 {
status = "disabled";
#phy-cells = <0>;
};
};
};
};
ports {
usb2-0 {
status = "disabled";
};
usb2-1 {
status = "disabled";
};
usb2-2 {
status = "disabled";
};
usb2-3 {
status = "disabled";
};
hsic-0 {
status = "disabled";
};
usb3-0 {
status = "disabled";
};
usb3-1 {
status = "disabled";
};
usb3-2 {
status = "disabled";
};
usb3-3 {
status = "disabled";
};
};
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sdhci@700b0000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sdhci@700b0200 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sdhci@700b0400 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sdhci@700b0600 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
mipi: mipi@700e3000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-mipi";
reg = <0x0 0x700e3000 0x0 0x100>;
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
arm64: tegra: Add SOR power-domain for Tegra210 Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:18 +07:00
power-domains = <&pd_sor>;
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
#nvidia,mipi-calibrate-cells = <1>;
};
arm64: tegra: Add ACONNECT bus node for Tegra210 Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17 19:40:34 +07:00
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
status = "disabled";
arm64: tegra: Add AGIC node for Tegra210 Populate the Audio GIC (AGIC) node for Tegra210. This interrupt controller is used by the Audio Processing Engine to route interrupts to the main CPU interrupt controller. The AGIC is based on the ARM GIC400 and so uses the clock name "clk" as specified by the GIC binding document for GIC400 devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:16 +07:00
arm64: tegra: Add ADMA node for Tegra210 Populate the ADMA node for Tegra210. The ADMA is used by the Audio Processing Engine (APE) on Tegra210 for moving data between the APE and system memory. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:17 +07:00
adma: dma@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x702e2000 0x2000>;
interrupt-parent = <&agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
status = "disabled";
};
arm64: tegra: Add AGIC node for Tegra210 Populate the Audio GIC (AGIC) node for Tegra210. This interrupt controller is used by the Audio Processing Engine to route interrupts to the main CPU interrupt controller. The AGIC is based on the ARM GIC400 and so uses the clock name "clk" as specified by the GIC binding document for GIC400 devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-09 22:21:16 +07:00
agic: agic@702f9000 {
compatible = "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x702f9000 0x2000>,
<0x702fa000 0x2000>;
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA210_CLK_APE>;
clock-names = "clk";
status = "disabled";
};
arm64: tegra: Add ACONNECT bus node for Tegra210 Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17 19:40:34 +07:00
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
spi@70410000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_QSPI>;
clock-names = "qspi";
resets = <&tegra_car 211>;
reset-names = "qspi";
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
usb@7d000000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USBD>;
clock-names = "usb";
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,phy = <&phy1>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
phy1: usb-phy@7d000000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USBD>,
<&tegra_car TEGRA210_CLK_PLL_U>,
<&tegra_car TEGRA210_CLK_USBD>;
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <0>;
nvidia,xcvr-lsrslew = <3>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
usb@7d004000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USB2>;
clock-names = "usb";
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
status = "disabled";
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
phy2: usb-phy@7d004000 {
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USB2>,
<&tegra_car TEGRA210_CLK_PLL_U>,
<&tegra_car TEGRA210_CLK_USBD>;
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <0>;
nvidia,xcvr-lsrslew = <3>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
status = "disabled";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <3>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra210-soctherm";
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
<&tegra_car TEGRA210_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
throttle-cfgs {
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
#cooling-cells = <2>;
};
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
};
thermal-zones {
cpu {
polling-delay-passive = <1000>;
polling-delay = <0>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
trips {
cpu-shutdown-trip {
temperature = <102500>;
hysteresis = <0>;
type = "critical";
};
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
cpu_throttle_trip: throttle-trip {
temperature = <98500>;
hysteresis = <1000>;
type = "hot";
};
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
};
cooling-maps {
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
map0 {
trip = <&cpu_throttle_trip>;
cooling-device = <&throttle_heavy 1 1>;
};
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
};
mem {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
trips {
mem-shutdown-trip {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
/*
* There are currently no cooling maps,
* because there are no cooling devices.
*/
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
};
gpu {
polling-delay-passive = <1000>;
polling-delay = <0>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
trips {
gpu-shutdown-trip {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
};
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
gpu_throttle_trip: throttle-trip {
temperature = <100000>;
hysteresis = <1000>;
type = "hot";
};
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
};
cooling-maps {
arm64: tegra: set hot trips for Tegra210 Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:26 +07:00
map0 {
trip = <&gpu_throttle_trip>;
cooling-device = <&throttle_heavy 1 1>;
};
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
};
pllx {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
arm64: tegra: set critical trips for Tegra210 Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:25 +07:00
trips {
pllx-shutdown-trip {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
/*
* There are currently no cooling maps,
* because there are no cooling devices.
*/
};
arm64: tegra: add soctherm node for Tegra210 Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-05-11 17:20:24 +07:00
};
};
arm64: tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 16:36:45 +07:00
};
Reference in New Issue Copy Permalink