linux_dsm_epyc7002/arch/x86/kernel/cpu
Kees Cook 873d50d58f x86/asm: Pin sensitive CR4 bits
Several recent exploits have used direct calls to the native_write_cr4()
function to disable SMEP and SMAP before then continuing their exploits
using userspace memory access.

Direct calls of this form can be mitigate by pinning bits of CR4 so that
they cannot be changed through a common function. This is not intended to
be a general ROP protection (which would require CFI to defend against
properly), but rather a way to avoid trivial direct function calling (or
CFI bypasses via a matching function prototype) as seen in:

https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-packet.html
(https://github.com/xairy/kernel-exploits/tree/master/CVE-2017-7308)

The goals of this change:

 - Pin specific bits (SMEP, SMAP, and UMIP) when writing CR4.

 - Avoid setting the bits too early (they must become pinned only after
   CPU feature detection and selection has finished).

 - Pinning mask needs to be read-only during normal runtime.

 - Pinning needs to be checked after write to validate the cr4 state

Using __ro_after_init on the mask is done so it can't be first disabled
with a malicious write.

Since these bits are global state (once established by the boot CPU and
kernel boot parameters), they are safe to write to secondary CPUs before
those CPUs have finished feature detection. As such, the bits are set at
the first cr4 write, so that cr4 write bugs can be detected (instead of
silently papered over). This uses a few bytes less storage of a location we
don't have: read-only per-CPU data.

A check is performed after the register write because an attack could just
skip directly to the register write. Such a direct jump is possible because
of how this function may be built by the compiler (especially due to the
removal of frame pointers) where it doesn't add a stack frame (function
exit may only be a retq without pops) which is sufficient for trivial
exploitation like in the timer overwrites mentioned above).

The asm argument constraints gain the "+" modifier to convince the compiler
that it shouldn't make ordering assumptions about the arguments or memory,
and treat them as changed.

Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: kernel-hardening@lists.openwall.com
Link: https://lkml.kernel.org/r/20190618045503.39105-3-keescook@chromium.org
2019-06-22 11:55:22 +02:00
..
mce treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441 2019-06-05 17:37:17 +02:00
microcode Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2019-06-16 07:28:14 -10:00
mtrr treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
resctrl Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2019-06-16 07:28:14 -10:00
.gitignore
amd.c x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor 2019-05-24 08:50:32 +02:00
aperfmperf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 437 2019-06-05 17:37:17 +02:00
bugs.c Merge branch 'x86-mds-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2019-05-14 07:57:29 -07:00
cacheinfo.c x86/kernel: Mark expected switch-case fall-throughs 2019-01-26 11:19:13 +01:00
centaur.c x86/CPU: Move x86_cpuinfo::x86_max_cores assignment to detect_num_cpu_cores() 2018-05-13 16:14:24 +02:00
common.c x86/asm: Pin sensitive CR4 bits 2019-06-22 11:55:22 +02:00
cpu.h PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handling 2019-04-07 22:33:19 +02:00
cpuid-deps.c x86/cpuid: Switch to 'static const' specifier 2018-03-08 12:23:42 +01:00
cyrix.c x86/cpu/cyrix: Use correct macros for Cyrix calls on Geode processors 2019-03-21 12:28:50 +01:00
hygon.c x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors 2019-03-23 17:41:09 +01:00
hypervisor.c x86/jailhouse: Add infrastructure for running in non-root cell 2018-01-14 21:11:54 +01:00
intel_epb.c x86: intel_epb: Do not build when CONFIG_PM is unset 2019-05-30 10:58:36 +02:00
intel_pconfig.c x86/pconfig: Detect PCONFIG targets 2018-03-12 12:10:54 +01:00
intel.c x86/cpu/intel: Lower the "ENERGY_PERF_BIAS: Set to normal" message's log priority 2019-04-19 19:23:13 +02:00
Makefile x86: intel_epb: Do not build when CONFIG_PM is unset 2019-05-30 10:58:36 +02:00
match.c x86/cpufeature: Add facility to check for min microcode revisions 2019-02-11 07:59:23 +01:00
mkcapflags.sh License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
mshyperv.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441 2019-06-05 17:37:17 +02:00
perfctr-watchdog.c x86/events: Add Hygon Dhyana support to PMU infrastructure 2018-09-27 18:28:57 +02:00
powerflags.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
proc.c x86: Convert some slow-path static_cpu_has() callers to boot_cpu_has() 2019-04-08 12:13:34 +02:00
rdrand.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 335 2019-06-05 17:37:06 +02:00
scattered.c Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2018-12-26 17:35:41 -08:00
topology.c x86/kernel: Fix more -Wmissing-prototypes warnings 2018-12-08 12:24:35 +01:00
transmeta.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
umc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
vmware.c x86/cpu/vmware: Do not trace vmware_sched_clock() 2018-11-09 21:39:14 +01:00