linux_dsm_epyc7002/drivers/gpu/drm/msm
Archit Taneja 8480adacfd drm/msm/mdp5: Assign 'right' mixer to CRTC state
Dynamically assign a right mixer to mdp5_crtc_state in the CRTC's
atomic_check path. Assigning the right mixer has some constraints,
i.e, only a few LMs can be paired together. Update mdp5_mixer_assign
to handle these constraints.

Firstly, we need to identify whether we need a right mixer or not.
At the moment, there are 2 scenarios where a right mixer might be
needed:
- If any of the planes connected to this CRTC is too wide (i.e, is
  comprised of 2 hwpipes).
- If the CRTC's mode itself is too wide (i.e, a 4K mode on HDMI).

We implement both these checks in the mdp5_crtc_atomic_check(), and
pass 'need_right_mixer' to mdp5_setup_pipeline.

If a CRTC is already assigned a single mixer, and a new atomic commit
brings in a drm_plane that needs 2 hwpipes, we can successfully commit
this mode without requiring a full modeset, provided that we still use
the previously assigned mixer as the left mixer. If such an assignment
isn't possible, we'd need to do a full modeset. This scenario has been
ignored for now.

The mixer assignment code is a bit messy, considering we have at most
4 LM instances in hardware. This can probably be re-visited later with
simplified logic.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-08 06:59:36 -04:00
..
adreno drm/msm: Pass interrupt status to a5xx_rbbm_err_irq() 2017-04-08 06:59:32 -04:00
dsi drm/msm/dsi: Fix bug in dsi_mgr_phy_enable 2017-04-08 06:59:32 -04:00
edp drm: bridge: Link encoder and bridge in core code 2016-12-18 16:31:45 +05:30
hdmi drm/msm/hdmi: redefinitions of macros not required 2017-04-08 06:59:33 -04:00
mdp drm/msm/mdp5: Assign 'right' mixer to CRTC state 2017-04-08 06:59:36 -04:00
Kconfig drm/msm/dsi: Add PHY/PLL for 8x96 2017-02-06 11:28:45 -05:00
Makefile drm/msm/mdp5: Add structs for hw Layer Mixers 2017-04-08 06:59:33 -04:00
msm_atomic.c drm/msm/mdp5: Add cursor planes 2017-02-06 11:28:44 -05:00
msm_debugfs.c drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_debugfs.h drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_drv.c drm/msm: Don't increase priv->num_aspaces until we know that it fits 2017-04-08 06:59:32 -04:00
msm_drv.h drm/msm: add stubs for msm_{perf,rd}_debugfs_cleanup 2017-03-20 15:34:01 +01:00
msm_fb.c drm: Nuke fb->pixel_format 2016-12-15 14:55:34 +02:00
msm_fbdev.c drm/fb-helper: Automatically clean up fb_info 2017-02-07 21:36:28 +01:00
msm_fence.c dma-buf: Rename struct fence to dma_fence 2016-10-25 14:40:39 +02:00
msm_fence.h dma-buf: Rename struct fence to dma_fence 2016-10-25 14:40:39 +02:00
msm_gem_prime.c drm/msm: change gem->vmap() to get/put 2016-07-16 10:09:07 -04:00
msm_gem_shrinker.c Merge branch 'linus' into locking/core, to pick up fixes 2016-11-22 12:37:38 +01:00
msm_gem_submit.c drm/msm: move submit fence wait out of struct_mutex 2017-04-08 06:59:31 -04:00
msm_gem_vma.c drm: Improve drm_mm search (and fix topdown allocation) with rbtrees 2017-02-03 11:10:32 +01:00
msm_gem.c drm/msm: Don't allow zero sized buffer objects 2017-04-08 06:59:32 -04:00
msm_gem.h drm/msm: convert iova to 64b 2016-11-28 15:14:08 -05:00
msm_gpu.c drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_gpu.h drm/msm/gpu: use pm-runtime 2017-04-08 06:59:31 -04:00
msm_iommu.c drm/msm: pm runtime support for iommu 2017-04-08 06:59:31 -04:00
msm_kms.h drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_mmu.h drm/msm: let gpu wire up it's own fault handler 2017-02-06 11:28:42 -05:00
msm_perf.c drm/msm: Remove msm_debugfs_cleanup() 2017-03-08 11:24:45 +01:00
msm_rd.c drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR 2017-04-08 06:59:32 -04:00
msm_ringbuffer.c drm/msm: Ensure that the hardware write pointer is valid 2016-12-29 15:02:58 -05:00
msm_ringbuffer.h drm/msm: add a3xx gpu support 2013-08-24 14:57:18 -04:00
NOTES drm/msm: add mdp5/apq8x74 2014-01-09 14:44:06 -05:00