mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 16:46:41 +07:00
77ad9dfc2c
This moves the set-up of the HREF500 with its AB8505 ASIC to a device tree include. Since there is not yet any device tree for this board the DTSI is currently unused. After this delete the board file for pins for good and migration of pins to the device tree is complete. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
241 lines
5.3 KiB
Plaintext
241 lines
5.3 KiB
Plaintext
/*
|
|
* Copyright 2014 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
/ {
|
|
soc {
|
|
prcmu@80157000 {
|
|
ab8505 {
|
|
ab8505-gpio {
|
|
/* Hog a few default settings */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&gpio2_default_mode>,
|
|
<&gpio10_default_mode>,
|
|
<&gpio11_default_mode>,
|
|
<&gpio13_default_mode>,
|
|
<&gpio34_default_mode>,
|
|
<&gpio50_default_mode>,
|
|
<&pwm_default_mode>,
|
|
<&adi2_default_mode>,
|
|
<&modsclsda_default_mode>,
|
|
<&resethw_default_mode>,
|
|
<&service_default_mode>;
|
|
|
|
/*
|
|
* Pins 2, 10, 11, 13, 34 and 50
|
|
* are muxed in as GPIO, and configured as INPUT PULL DOWN
|
|
*/
|
|
gpio2 {
|
|
gpio2_default_mode: gpio2_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio2_a_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO2_R5";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
gpio10 {
|
|
gpio10_default_mode: gpio10_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio10_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO10_B16";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
gpio11 {
|
|
gpio11_default_mode: gpio11_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio11_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO11_B17";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
gpio13 {
|
|
gpio13_default_mode: gpio13_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio13_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO13_D17";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
gpio34 {
|
|
gpio34_default_mode: gpio34_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio34_a_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO34_H14";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
gpio50 {
|
|
gpio50_default_mode: gpio50_default {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio50_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO50_L4";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
/* This sets up the PWM pin 14 */
|
|
pwm {
|
|
pwm_default_mode: pwm_default {
|
|
default_mux {
|
|
ste,function = "pwmout";
|
|
ste,pins = "pwmout1_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO14_C16";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
/* This sets up audio interface 2 */
|
|
adi2 {
|
|
adi2_default_mode: adi2_default {
|
|
default_mux {
|
|
ste,function = "adi2";
|
|
ste,pins = "adi2_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO17_P2",
|
|
"GPIO18_N3",
|
|
"GPIO19_T1",
|
|
"GPIO20_P3";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
/* Modem I2C setup (SCL and SDA pins) */
|
|
modsclsda {
|
|
modsclsda_default_mode: modsclsda_default {
|
|
default_mux {
|
|
ste,function = "modsclsda";
|
|
ste,pins = "modsclsda_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO40_J15",
|
|
"GPIO41_J14";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
resethw {
|
|
resethw_default_mode: resethw_default {
|
|
default_mux {
|
|
ste,function = "resethw";
|
|
ste,pins = "resethw_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO52_D16";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
service {
|
|
service_default_mode: service_default {
|
|
default_mux {
|
|
ste,function = "service";
|
|
ste,pins = "service_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO53_D15";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
/*
|
|
* Clock output pins associated with regulators.
|
|
*/
|
|
sysclkreq2 {
|
|
sysclkreq2_default_mode: sysclkreq2_default {
|
|
default_mux {
|
|
ste,function = "sysclkreq";
|
|
ste,pins = "sysclkreq2_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO1_N4";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
sysclkreq2_sleep_mode: sysclkreq2_sleep {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio1_a_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO1_N4";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
sysclkreq4 {
|
|
sysclkreq4_default_mode: sysclkreq4_default {
|
|
default_mux {
|
|
ste,function = "sysclkreq";
|
|
ste,pins = "sysclkreq4_d_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO3_P5";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
sysclkreq4_sleep_mode: sysclkreq4_sleep {
|
|
default_mux {
|
|
ste,function = "gpio";
|
|
ste,pins = "gpio3_a_1";
|
|
};
|
|
default_cfg {
|
|
ste,pins = "GPIO3_P5";
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|