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72296bde4f
Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC based around the SiFive U54-MC core complex and a TileLink interconnect. This file is expected to grow as more device drivers are added to the kernel. This patch includes a fix to the QSPI memory map due to a documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds entries for the I2C controller, and merges all DT changes that formerly were made dynamically by the riscv-pk BBL proxy kernel. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Loys Ollivier <lollivier@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: ShihPo Hung <shihpo.hung@sifive.com> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org
216 lines
5.3 KiB
Plaintext
216 lines
5.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2018-2019 SiFive, Inc */
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/dts-v1/;
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,fu540-c000", "sifive,fu540";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu0: cpu@0 {
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
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ranges;
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,ndev = <53>;
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff
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&cpu1_intc 0xffffffff &cpu1_intc 9
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&cpu2_intc 0xffffffff &cpu2_intc 9
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&cpu3_intc 0xffffffff &cpu3_intc 9
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&cpu4_intc 0xffffffff &cpu4_intc 9>;
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};
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prci: clock-controller@10000000 {
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compatible = "sifive,fu540-c000-prci";
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reg = <0x0 0x10000000 0x0 0x1000>;
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clocks = <&hfclk>, <&rtcclk>;
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#clock-cells = <1>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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reg = <0x0 0x10010000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <4>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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};
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uart1: serial@10011000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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reg = <0x0 0x10011000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <5>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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};
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i2c0: i2c@10030000 {
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compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
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reg = <0x0 0x10030000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <50>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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qspi0: spi@10040000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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reg = <0x0 0x10040000 0x0 0x1000
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0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <51>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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qspi1: spi@10041000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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reg = <0x0 0x10041000 0x0 0x1000
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0x0 0x30000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <52>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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qspi2: spi@10050000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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reg = <0x0 0x10050000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <6>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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