Paul Walmsley 72296bde4f riscv: dts: add initial support for the SiFive FU540-C000 SoC ... Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC based around the SiFive U54-MC core complex and a TileLink interconnect. This file is expected to grow as more device drivers are added to the kernel. This patch includes a fix to the QSPI memory map due to a documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds entries for the I2C controller, and merges all DT changes that formerly were made dynamically by the riscv-pk BBL proxy kernel. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Loys Ollivier <lollivier@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: ShihPo Hung <shihpo.hung@sifive.com> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org		2019-06-17 02:04:05 -07:00
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dts	riscv: dts: add initial support for the SiFive FU540-C000 SoC	2019-06-17 02:04:05 -07:00
.gitignore	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00
install.sh	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00
Makefile	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00