AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
6bd33e1ece
linux_dsm_epyc7002/arch/riscv/include/asm
History
Christoph Hellwig 6bd33e1ece riscv: add nommu support 
The kernel runs in M-mode without using page tables, and thus can't run
bare metal without help from additional firmware.

Most of the patch is just stubbing out code not needed without page
tables, but there is an interesting detail in the signals implementation:

 - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO
   entry point, but the ELF VDSO is not supported for nommu Linux.
   We instead copy the code to call the syscall onto the stack.

In addition to enabling the nommu code a new defconfig for a small
kernel image that can run in nommu mode on qemu is also provided, to run
a kernel in qemu you can use the following command line:

qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \
	-kernel arch/riscv/boot/loader \
	-drive file=rootfs.ext2,format=raw,id=hd0 \
	-device virtio-blk-device,drive=hd0

Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards
 around PCI_IOBASE definition to fix build issues; fixed checkpatch
 issues; move the PCI_IO_* and VMEMMAP address space macros along
 with the others; resolve sparse warning]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-11-17 15:17:39 -08:00
..
asm-offsets.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
asm-prototypes.h RISC-V: include linux/ftrace.h in asm-prototypes.h 2018-09-24 13:12:27 -07:00
asm.h RISC-V: Clear load reservations while restoring hart contexts 2019-10-01 13:16:40 -07:00
atomic.h locking/atomic, riscv: Use s64 for atomic64 2019-06-03 12:32:56 +02:00
barrier.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 2019-06-19 17:09:07 +02:00
bitops.h RISC-V patches for v5.2-rc6 2019-06-17 10:34:03 -07:00
bug.h riscv: cleanup <asm/bug.h> 2019-10-23 14:53:46 -07:00
cache.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
cacheflush.h riscv: fix build break after macro-to-function conversion in generic cacheflush.h 2019-07-18 08:16:56 -07:00
clint.h riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
cmpxchg.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
csr.h riscv: clear the instruction cache and all registers when booting 2019-11-17 15:17:39 -08:00
current.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
delay.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
elf.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
fence.h riscv/spinlock: Strengthen implementations with fences 2018-04-02 19:59:43 -07:00
fixmap.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
ftrace.h riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
futex.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
hugetlb.h riscv: Introduce huge page support for 32/64bit kernel 2019-07-03 15:23:38 -07:00
hwcap.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 2019-06-19 17:09:07 +02:00
image.h riscv: modify the Image header to improve compatibility with the ARM64 header 2019-09-13 19:03:52 -07:00
io.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
irq.h riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
irqflags.h riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
Kbuild riscv: include generic support for MSI irqdomains 2019-07-22 13:06:07 -07:00
kprobes.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 2019-05-30 11:26:41 -07:00
linkage.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
mmio.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
mmiowb.h riscv/mmiowb: Hook up mmwiob() implementation to asm-generic code 2019-04-08 12:00:40 +01:00
mmu_context.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
mmu.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
module.h RISC-V: Support MODULE_SECTIONS mechanism on RV32 2019-01-07 08:19:20 -08:00
page.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
pci.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
perf_event.h RISC-V: Fix !CONFIG_SMP compilation error 2018-08-13 08:31:32 -07:00
pgalloc.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
pgtable-32.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
pgtable-64.h RISC-V: Setup initial page tables in two stages 2019-07-09 09:08:04 -07:00
pgtable-bits.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
pgtable.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
processor.h riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
ptrace.h riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
sbi.h riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
sifive_l2_cache.h RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs 2019-05-16 20:42:13 -07:00
smp.h riscv: cleanup riscv_cpuid_to_hartid_mask 2019-09-05 01:51:57 -07:00
sparsemem.h RISC-V: Implement sparsemem 2019-08-30 11:10:37 -07:00
spinlock_types.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
spinlock.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
string.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
switch_to.h riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
syscall.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
thread_info.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
timex.h riscv: add support for MMIO access to the timer registers 2019-11-13 14:10:40 -08:00
tlb.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
tlbflush.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
uaccess.h riscv: add nommu support 2019-11-17 15:17:39 -08:00
unistd.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
vdso.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 2019-06-19 17:09:07 +02:00
word-at-a-time.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00