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locking/atomic, riscv: Use s64 for atomic64
As a step towards making the atomic64 API use consistent types treewide, let's have the RISC-V atomic64 implementation use s64 as the underlying type for atomic64_t, rather than long, matching the generated headers. As atomic64_read() depends on the generic defintion of atomic64_t, this still returns long on 64-bit. This will be converted in a subsequent patch. Otherwise, there should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Cc: arnd@arndb.de Cc: bp@alien8.de Cc: catalin.marinas@arm.com Cc: davem@davemloft.net Cc: fenghua.yu@intel.com Cc: heiko.carstens@de.ibm.com Cc: herbert@gondor.apana.org.au Cc: ink@jurassic.park.msu.ru Cc: jhogan@kernel.org Cc: linux@armlinux.org.uk Cc: mattst88@gmail.com Cc: mpe@ellerman.id.au Cc: paul.burton@mips.com Cc: paulus@samba.org Cc: ralf@linux-mips.org Cc: rth@twiddle.net Cc: tony.luck@intel.com Cc: vgupta@synopsys.com Link: https://lkml.kernel.org/r/20190522132250.26499-13-mark.rutland@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -38,11 +38,11 @@ static __always_inline void atomic_set(atomic_t *v, int i)
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC64_INIT(i) { (i) }
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static __always_inline long atomic64_read(const atomic64_t *v)
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static __always_inline s64 atomic64_read(const atomic64_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void atomic64_set(atomic64_t *v, long i)
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static __always_inline void atomic64_set(atomic64_t *v, s64 i)
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{
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WRITE_ONCE(v->counter, i);
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}
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@ -66,11 +66,11 @@ void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, )
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ATOMIC_OP (op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_OP (op, asm_op, I, w, int, ) \
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ATOMIC_OP (op, asm_op, I, d, long, 64)
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ATOMIC_OP (op, asm_op, I, w, int, ) \
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ATOMIC_OP (op, asm_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(add, add, i)
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@ -127,14 +127,14 @@ c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, )
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, d, long, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, d, long, 64)
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ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) \
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ATOMIC_FETCH_OP( op, asm_op, I, d, s64, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(add, add, +, i)
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@ -166,11 +166,11 @@ ATOMIC_OPS(sub, add, +, -i)
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, )
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, I) \
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) \
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ATOMIC_FETCH_OP(op, asm_op, I, d, long, 64)
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ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) \
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ATOMIC_FETCH_OP(op, asm_op, I, d, s64, 64)
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#endif
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ATOMIC_OPS(and, and, i)
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@ -219,9 +219,10 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long atomic64_fetch_add_unless(atomic64_t *v, long a, long u)
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static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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{
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long prev, rc;
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s64 prev;
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long rc;
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__asm__ __volatile__ (
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"0: lr.d %[p], %[c]\n"
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@ -290,11 +291,11 @@ c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS() \
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ATOMIC_OP( int, , 4)
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ATOMIC_OP(int, , 4)
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#else
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#define ATOMIC_OPS() \
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ATOMIC_OP( int, , 4) \
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ATOMIC_OP(long, 64, 8)
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ATOMIC_OP(int, , 4) \
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ATOMIC_OP(s64, 64, 8)
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#endif
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ATOMIC_OPS()
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@ -332,9 +333,10 @@ static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset)
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#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1)
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long atomic64_sub_if_positive(atomic64_t *v, long offset)
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static __always_inline s64 atomic64_sub_if_positive(atomic64_t *v, s64 offset)
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{
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long prev, rc;
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s64 prev;
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long rc;
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__asm__ __volatile__ (
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"0: lr.d %[p], %[c]\n"
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