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6b0b8ccff0
Instead of having three different clocks for the main MMC clock and the two phase sub-clocks, which involved having three different drivers sharing the same register, rework it to have the same single driver registering three different clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Mike Turquette <mturquette@linaro.org> |
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.. | ||
clk-a10-hosc.c | ||
clk-a20-gmac.c | ||
clk-factors.c | ||
clk-factors.h | ||
clk-mod0.c | ||
clk-sun6i-apb0-gates.c | ||
clk-sun6i-apb0.c | ||
clk-sun6i-ar100.c | ||
clk-sun8i-apb0.c | ||
clk-sun8i-mbus.c | ||
clk-sun9i-core.c | ||
clk-sunxi.c | ||
Makefile |