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787fd1d019
We currently copy the physical address size from ID_AA64MMFR0_EL1.PARange directly into TCR.(I)PS. This will not work for 4k and 16k granule kernels on systems that support 52-bit physical addresses, since 52-bit addresses are only permitted with the 64k granule. To fix this, fall back to 48 bits when configuring the PA size when the kernel does not support 52-bit PAs. When it does, fall back to 52, to avoid similar problems in the future if the PA size is ever increased above 52. Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Bob Picco <bob.picco@oracle.com> Reviewed-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> [catalin.marinas@arm.com: tcr_set_pa_size macro renamed to tcr_compute_pa_size] [catalin.marinas@arm.com: comments added to tcr_compute_pa_size] [catalin.marinas@arm.com: definitions added for TCR_*PS_SHIFT] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
91 lines
2.2 KiB
C
91 lines
2.2 KiB
C
/*
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* Copyright (C) 2016 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_hyp.h>
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u32 __hyp_text __init_stage2_translation(void)
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{
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u64 val = VTCR_EL2_FLAGS;
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u64 parange;
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u64 tmp;
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS
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* bits in VTCR_EL2. Amusingly, the PARange is 4 bits, while
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* PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2...
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*/
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parange = read_sysreg(id_aa64mmfr0_el1) & 7;
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if (parange > ID_AA64MMFR0_PARANGE_MAX)
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parange = ID_AA64MMFR0_PARANGE_MAX;
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val |= parange << 16;
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/* Compute the actual PARange... */
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switch (parange) {
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case 0:
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parange = 32;
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break;
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case 1:
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parange = 36;
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break;
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case 2:
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parange = 40;
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break;
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case 3:
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parange = 42;
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break;
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case 4:
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parange = 44;
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break;
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case 5:
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default:
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parange = 48;
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break;
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}
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/*
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* ... and clamp it to 40 bits, unless we have some braindead
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* HW that implements less than that. In all cases, we'll
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* return that value for the rest of the kernel to decide what
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* to do.
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*/
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val |= 64 - (parange > 40 ? 40 : parange);
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/*
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* Check the availability of Hardware Access Flag / Dirty Bit
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* Management in ID_AA64MMFR1_EL1 and enable the feature in VTCR_EL2.
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*/
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tmp = (read_sysreg(id_aa64mmfr1_el1) >> ID_AA64MMFR1_HADBS_SHIFT) & 0xf;
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if (tmp)
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val |= VTCR_EL2_HA;
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/*
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* Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS
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* bit in VTCR_EL2.
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*/
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tmp = (read_sysreg(id_aa64mmfr1_el1) >> ID_AA64MMFR1_VMIDBITS_SHIFT) & 0xf;
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val |= (tmp == ID_AA64MMFR1_VMIDBITS_16) ?
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VTCR_EL2_VS_16BIT :
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VTCR_EL2_VS_8BIT;
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write_sysreg(val, vtcr_el2);
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return parange;
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}
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