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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/barrier.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2013 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_BARRIER_H
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#define _ASM_RISCV_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__ ("nop")
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw,iorw)
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#define rmb() RISCV_FENCE(ir,ir)
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#define wmb() RISCV_FENCE(ow,ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define __smp_mb() RISCV_FENCE(rw,rw)
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#define __smp_rmb() RISCV_FENCE(r,r)
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#define __smp_wmb() RISCV_FENCE(w,w)
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(rw,w); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(r,rw); \
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___p1; \
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})
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/*
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* This is a very specific barrier: it's currently only used in two places in
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* the kernel, both in the scheduler. See include/linux/spinlock.h for the two
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* orderings it guarantees, but the "critical section is RCsc" guarantee
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* mandates a barrier on RISC-V. The sequence looks like:
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*
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* lr.aq lock
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* sc lock <= LOCKED
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* smp_mb__after_spinlock()
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* // critical section
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* lr lock
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* sc.rl lock <= UNLOCKED
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*
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* The AQ/RL pair provides a RCpc critical section, but there's not really any
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* way we can take advantage of that here because the ordering is only enforced
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* on that one lock. Thus, we're just doing a full fence.
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*/
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#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw)
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_BARRIER_H */
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