James Zhu 5326ad54c5 drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled ... When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-05-24 12:20:50 -05:00
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drm	drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled	2019-05-24 12:20:50 -05:00
host1x	gpu: host1x: Program stream ID to bypass without SMMU	2019-04-11 17:40:35 +02:00
ipu-v3	gpu: ipu-v3: dp: fix CSC handling	2019-04-23 14:54:16 +02:00
vga	- qxl: Remove the conflicting framebuffers earlier	2019-03-14 11:37:46 +10:00
Makefile