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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
Alex Deucher
parent
8511477773
commit
5326ad54c5
@ -34,6 +34,7 @@
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#include "vega10_enum.h"
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#include "hdp/hdp_4_0_offset.h"
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#include "soc15.h"
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#include "soc15_common.h"
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#include "clearstate_gfx9.h"
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#include "v9_structs.h"
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@ -3529,6 +3530,245 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
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(1 << (oa_size + oa_base)) - (1 << oa_base));
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}
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static const u32 vgpr_init_compute_shader[] =
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{
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0xb07c0000, 0xbe8000ff,
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0x000000f8, 0xbf110800,
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0x7e000280, 0x7e020280,
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0x7e040280, 0x7e060280,
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0x7e080280, 0x7e0a0280,
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0x7e0c0280, 0x7e0e0280,
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0x80808800, 0xbe803200,
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0xbf84fff5, 0xbf9c0000,
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0xd28c0001, 0x0001007f,
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0xd28d0001, 0x0002027e,
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0x10020288, 0xb8810904,
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0xb7814000, 0xd1196a01,
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0x00000301, 0xbe800087,
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0xbefc00c1, 0xd89c4000,
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0x00020201, 0xd89cc080,
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0x00040401, 0x320202ff,
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0x00000800, 0x80808100,
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0xbf84fff8, 0x7e020280,
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0xbf810000, 0x00000000,
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};
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static const u32 sgpr_init_compute_shader[] =
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{
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0xb07c0000, 0xbe8000ff,
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0x0000005f, 0xbee50080,
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0xbe812c65, 0xbe822c65,
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0xbe832c65, 0xbe842c65,
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0xbe852c65, 0xb77c0005,
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0x80808500, 0xbf84fff8,
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0xbe800080, 0xbf810000,
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};
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static const struct soc15_reg_entry vgpr_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
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};
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static const struct soc15_reg_entry sgpr_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
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};
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static const struct soc15_reg_entry sec_ded_counter_registers[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED) },
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{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2) },
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{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT) },
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};
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static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
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struct amdgpu_ib ib;
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struct dma_fence *f = NULL;
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int r, i, j;
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u32 tmp;
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unsigned total_size, vgpr_offset, sgpr_offset;
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u64 gpu_addr;
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/* only support when RAS is enabled */
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
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return 0;
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/* bail if the compute ring is not ready */
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if (!ring->sched.ready)
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return 0;
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tmp = RREG32_SOC15(GC, 0, mmGB_EDC_MODE);
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WREG32_SOC15(GC, 0, mmGB_EDC_MODE, 0);
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total_size =
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((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
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total_size +=
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((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
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total_size = ALIGN(total_size, 256);
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vgpr_offset = total_size;
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total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
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sgpr_offset = total_size;
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total_size += sizeof(sgpr_init_compute_shader);
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/* allocate an indirect buffer to put the commands in */
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memset(&ib, 0, sizeof(ib));
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r = amdgpu_ib_get(adev, NULL, total_size, &ib);
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if (r) {
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DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
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return r;
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}
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/* load the compute shaders */
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for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
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ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
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for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
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ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
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/* init the ib length to 0 */
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ib.length_dw = 0;
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/* VGPR */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i++) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs[i])
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = vgpr_init_regs[i].reg_value;
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 128; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* SGPR */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(sgpr_init_regs); i++) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr_init_regs[i])
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = sgpr_init_regs[i].reg_value;
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 128; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* shedule the ib on the ring */
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r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
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if (r) {
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DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
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goto fail;
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}
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/* wait for the GPU to finish processing the IB */
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r = dma_fence_wait(f, false);
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if (r) {
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DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
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goto fail;
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}
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/* read back registers to clear the counters */
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mutex_lock(&adev->grbm_idx_mutex);
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for (j = 0; j < 16; j++) {
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gfx_v9_0_select_se_sh(adev, 0x01, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x02, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x03, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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gfx_v9_0_select_se_sh(adev, 0x04, 0x0, j);
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
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}
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WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
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mutex_unlock(&adev->grbm_idx_mutex);
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fail:
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amdgpu_ib_free(adev, &ib, NULL);
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dma_fence_put(f);
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return r;
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}
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static int gfx_v9_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -3577,6 +3817,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
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if (!*ras_if)
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return -ENOMEM;
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/* requires IBs so do in late init after IB pool is initialized */
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r = gfx_v9_0_do_edc_gpr_workarounds(adev);
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if (r)
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return r;
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**ras_if = ras_block;
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r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
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@ -42,8 +42,18 @@ struct soc15_reg_golden {
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u32 or_mask;
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};
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struct soc15_reg_entry {
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uint32_t hwip;
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uint32_t inst;
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uint32_t seg;
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uint32_t reg_offset;
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uint32_t reg_value;
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};
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#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
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#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
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#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
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{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
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