mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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513b67ac39
mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
92 lines
3.5 KiB
C
92 lines
3.5 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MESON8B_H
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#define __MESON8B_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
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#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
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#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
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#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
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#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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/*
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* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
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* confirm these are the same for the S805.
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*/
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
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#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
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#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
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#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
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#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
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#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
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#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
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#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
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#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_MPLL0_DIV 96
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#define CLKID_MPLL1_DIV 97
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#define CLKID_MPLL2_DIV 98
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#define CLKID_CPU_IN_SEL 99
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#define CLKID_CPU_DIV2 100
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#define CLKID_CPU_DIV3 101
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#define CLKID_CPU_SCALE_DIV 102
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#define CLKID_CPU_SCALE_OUT_SEL 103
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#define CLKID_MPLL_PREDIV 104
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#define CLK_NR_CLKS 105
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/*
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* include the CLKID and RESETID that have
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* been made part of the stable DT binding
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*/
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#endif /* __MESON8B_H */
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