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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 00:46:21 +07:00
clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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093c3fac46
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513b67ac39
@ -354,6 +354,20 @@ static struct clk_fixed_factor axg_fclk_div7 = {
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},
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};
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static struct clk_regmap axg_mpll_prediv = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MPLL_CNTL5,
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.shift = 12,
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.width = 1,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll_prediv",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap axg_mpll0_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
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@ -386,7 +400,7 @@ static struct clk_regmap axg_mpll0_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll0_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -432,7 +446,7 @@ static struct clk_regmap axg_mpll1_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll1_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -478,7 +492,7 @@ static struct clk_regmap axg_mpll2_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll2_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -524,7 +538,7 @@ static struct clk_regmap axg_mpll3_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll3_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -821,6 +835,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
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[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
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[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
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[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
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[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -893,6 +908,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
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&axg_sys_pll,
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&axg_gp0_pll,
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&axg_hifi_pll,
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&axg_mpll_prediv,
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};
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static const struct of_device_id clkc_match_table[] = {
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@ -121,8 +121,9 @@
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#define CLKID_MPLL1_DIV 66
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#define CLKID_MPLL2_DIV 67
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#define CLKID_MPLL3_DIV 68
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#define CLKID_MPLL_PREDIV 70
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#define NR_CLKS 70
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#define NR_CLKS 71
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/axg-clkc.h>
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@ -545,6 +545,20 @@ static struct clk_fixed_factor gxbb_fclk_div7 = {
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},
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};
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static struct clk_regmap gxbb_mpll_prediv = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MPLL_CNTL5,
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.shift = 12,
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.width = 1,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll_prediv",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap gxbb_mpll0_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
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@ -572,7 +586,7 @@ static struct clk_regmap gxbb_mpll0_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll0_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -613,7 +627,7 @@ static struct clk_regmap gxbb_mpll1_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll1_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -654,7 +668,7 @@ static struct clk_regmap gxbb_mpll2_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll2_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -1703,6 +1717,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
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[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
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[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
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[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -1853,6 +1868,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
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[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
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[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
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[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -2005,6 +2021,7 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
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&gxbb_cts_amclk_div,
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&gxbb_fixed_pll,
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&gxbb_sys_pll,
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&gxbb_mpll_prediv,
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};
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struct clkc_data {
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@ -198,8 +198,9 @@
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#define CLKID_MPLL0_DIV 142
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#define CLKID_MPLL1_DIV 143
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#define CLKID_MPLL2_DIV 144
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#define CLKID_MPLL_PREDIV 145
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#define NR_CLKS 145
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#define NR_CLKS 146
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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@ -280,6 +280,20 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
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},
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};
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static struct clk_regmap meson8b_mpll_prediv = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MPLL_CNTL5,
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.shift = 12,
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.width = 1,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll_prediv",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap meson8b_mpll0_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
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@ -307,7 +321,7 @@ static struct clk_regmap meson8b_mpll0_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll0_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -348,7 +362,7 @@ static struct clk_regmap meson8b_mpll1_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll1_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -389,7 +403,7 @@ static struct clk_regmap meson8b_mpll2_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll2_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_names = (const char *[]){ "mpll_prediv" },
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.num_parents = 1,
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},
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};
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@ -751,6 +765,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw,
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[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
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[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
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[CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -850,6 +865,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8b_cpu_scale_div,
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&meson8b_cpu_scale_out_sel,
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&meson8b_cpu_clk,
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&meson8b_mpll_prediv,
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};
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static const struct meson8b_clk_reset_line {
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@ -77,8 +77,9 @@
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#define CLKID_CPU_DIV3 101
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#define CLKID_CPU_SCALE_DIV 102
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#define CLKID_CPU_SCALE_OUT_SEL 103
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#define CLKID_MPLL_PREDIV 104
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#define CLK_NR_CLKS 104
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#define CLK_NR_CLKS 105
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/*
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* include the CLKID and RESETID that have
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