Roger Quadros 1d1bae7250 phy: ti-pipe3: Fix PCIe power up sequence ... TRM [1] mentions that we need to power up PCIESS_PHY_TX and PCIESS_PHY_RX before configuring PCIe_PHY_RX SCP settings. See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>		2019-04-17 14:13:07 +05:30
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Kconfig	phy: for 5.1	2019-02-12 14:59:43 +01:00
Makefile	phy: ti: introduce phy-gmii-sel driver	2018-12-12 10:01:40 +05:30
phy-da8xx-usb.c	phy: core: rework phy_set_mode to accept phy mode and submode	2018-12-12 10:01:33 +05:30
phy-dm816x-usb.c
phy-gmii-sel.c	phy: ti: ensure priv is not null before dereferencing it	2019-01-16 18:00:54 +05:30
phy-omap-control.c
phy-omap-usb2.c	phy: ti: usb2: Add support for AM654 USB2 PHY	2019-02-07 11:10:41 +05:30
phy-ti-pipe3.c	phy: ti-pipe3: Fix PCIe power up sequence	2019-04-17 14:13:07 +05:30
phy-tusb1210.c	phy: core: rework phy_set_mode to accept phy mode and submode	2018-12-12 10:01:33 +05:30
phy-twl4030-usb.c	phy: phy-twl4030-usb: fix denied runtime access	2018-09-25 16:10:12 +05:30