mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 11:45:01 +07:00
d893c4de01
This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure. At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module. - https://www.spinics.net/lists/arm-kernel/msg613212.html After checking again the L2 cache use in the NPCM7xx, the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree: https://patchwork.kernel.org/patch/10063497/ L2 cache flag mask allowed all the flag option. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
23 lines
533 B
C
23 lines
533 B
C
// SPDX-License-Identifier: GPL-2.0
|
|
// Copyright (c) 2018 Nuvoton Technology corporation.
|
|
// Copyright 2018 Google, Inc.
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/types.h>
|
|
#include <asm/mach/arch.h>
|
|
#include <asm/mach-types.h>
|
|
#include <asm/mach/map.h>
|
|
#include <asm/hardware/cache-l2x0.h>
|
|
|
|
static const char *const npcm7xx_dt_match[] = {
|
|
"nuvoton,npcm750",
|
|
NULL
|
|
};
|
|
|
|
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
|
|
.atag_offset = 0x100,
|
|
.dt_compat = npcm7xx_dt_match,
|
|
.l2c_aux_val = 0x0,
|
|
.l2c_aux_mask = ~0x0,
|
|
MACHINE_END
|