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arm: npcm: enable L2 cache in NPCM7xx architecture

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This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC
by adding L2 cache parameters into NPCM7xx DT machine start structure.

At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments
regarding the flags use in L2 cache module.
- https://www.spinics.net/lists/arm-kernel/msg613212.html

After checking again the L2 cache use in the NPCM7xx,
the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE
and it is done in the device tree:
https://patchwork.kernel.org/patch/10063497/

L2 cache flag mask allowed all the flag option.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Tomer Maimon 2018-04-08 17:03:17 +03:00 committed by Arnd Bergmann
parent 38c23685b2
commit d893c4de01
1 changed files with 2 additions and 0 deletions
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2
arch/arm/mach-npcm/npcm7xx.c
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@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,
MACHINE_END