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400816f60c
Skylake (and later) will receive a microcode update to address a TSX errata. This microcode will, on execution of a TSX instruction (speculative or not) use (clobber) PMC3. This update will also provide a new MSR to change this behaviour along with a CPUID bit to enumerate the presence of this new MSR. When the MSR gets set; the microcode will no longer use PMC3 but will Force Abort every TSX transaction (upon executing COMMIT). When TSX Force Abort (TFA) is allowed (default); the MSR gets set when PMC3 gets scheduled and cleared when, after scheduling, PMC3 is unused. When TFA is not allowed; clear PMC3 from all constraints such that it will not get used. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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| .. | ||
| bts.c | ||
| core.c | ||
| cstate.c | ||
| ds.c | ||
| knc.c | ||
| lbr.c | ||
| Makefile | ||
| p4.c | ||
| p6.c | ||
| pt.c | ||
| pt.h | ||
| rapl.c | ||
| uncore_nhmex.c | ||
| uncore_snb.c | ||
| uncore_snbep.c | ||
| uncore.c | ||
| uncore.h | ||