Peter Zijlstra (Intel) 400816f60c perf/x86/intel: Implement support for TSX Force Abort ... Skylake (and later) will receive a microcode update to address a TSX errata. This microcode will, on execution of a TSX instruction (speculative or not) use (clobber) PMC3. This update will also provide a new MSR to change this behaviour along with a CPUID bit to enumerate the presence of this new MSR. When the MSR gets set; the microcode will no longer use PMC3 but will Force Abort every TSX transaction (upon executing COMMIT). When TSX Force Abort (TFA) is allowed (default); the MSR gets set when PMC3 gets scheduled and cleared when, after scheduling, PMC3 is unused. When TFA is not allowed; clear PMC3 from all constraints such that it will not get used. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>		2019-03-06 09:25:41 +01:00
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amd	Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2018-10-23 16:16:40 +01:00
intel	perf/x86/intel: Implement support for TSX Force Abort	2019-03-06 09:25:41 +01:00
core.c	perf/x86/intel: Make cpuc allocations consistent	2019-03-06 09:25:40 +01:00
Kconfig	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
Makefile	perf/x86/events: Add an AMD-specific Makefile	2017-01-30 12:01:19 +01:00
msr.c	x86/cpu: Sanitize FAM6_ATOM naming	2018-10-02 10:14:32 +02:00
perf_event.h	perf/x86/intel: Implement support for TSX Force Abort	2019-03-06 09:25:41 +01:00