Nicolai Hähnle 38610f15a7 drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders ... Otherwise, the SQ may skip some of the register writes, or shader waves may be allocated where we don't expect them, so that as a result we don't actually reset all of the register SRAMs. This can lead to spurious ECC errors later on if a shader uses an uninitialized register. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2018-05-15 13:43:49 -05:00
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drm	drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders	2018-05-15 13:43:49 -05:00
host1x
ipu-v3	gpu: ipu-v3: prg: avoid possible array underflow	2018-03-15 17:52:08 +01:00
vga	vga_switcheroo: Let HDA autosuspend on mux change	2018-03-13 22:58:49 +01:00
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