AuxXxilium/linux_dsm_epyc7002
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328e1a633c
linux_dsm_epyc7002/drivers/gpu/drm/msm/dsi/pll
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Hai Li 328e1a633c drm/msm/dsi: Save/Restore PLL status across PHY reset 
Reset DSI PHY silently changes its PLL registers to reset status,
which will make cached status in clock driver invalid and result
in wrong output rate of link clocks. The current restore mechanism
in DSI PLL does not cover all the cases. This change is to recover
PLL status after PHY reset to match HW status with cached status
in clock driver.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-15 18:27:18 -04:00
..
dsi_pll_28nm.c drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00
dsi_pll.c drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00
dsi_pll.h drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00