Hai Li 328e1a633c drm/msm/dsi: Save/Restore PLL status across PHY reset ... Reset DSI PHY silently changes its PLL registers to reset status, which will make cached status in clock driver invalid and result in wrong output rate of link clocks. The current restore mechanism in DSI PLL does not cover all the cases. This change is to recover PLL status after PHY reset to match HW status with cached status in clock driver. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2015-08-15 18:27:18 -04:00
..
drm	drm/msm/dsi: Save/Restore PLL status across PHY reset	2015-08-15 18:27:18 -04:00
host1x	gpu: host1x: Export host1x_syncpt_read()	2015-04-02 18:46:20 +02:00
ipu-v3	GPU: ipu: fix lockup caused by pending chained interrupts	2015-07-10 11:02:46 +02:00
vga	vga_switcheroo: Remove unnecessary checks	2015-08-12 17:13:19 +02:00
Makefile