Andre Przywara 266068eabb KVM: arm/arm64: vgic-v2: Limit ITARGETSR bits to number of VCPUs ... The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI." Currently we allow the guest to write any value in there and it can read that back. Mask the written value with the proper CPU mask to be spec compliant. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2016-12-09 15:46:59 +00:00
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hyp	arm64: KVM: Move vgic-v3 save/restore to virt/kvm/arm/hyp	2016-09-22 13:21:46 +02:00
vgic	KVM: arm/arm64: vgic-v2: Limit ITARGETSR bits to number of VCPUs	2016-12-09 15:46:59 +00:00
aarch32.c	arm64: KVM: Make kvm_skip_instr32 available to HYP	2016-09-08 12:53:00 +02:00
arch_timer.c	arm/arm64: KVM: Clean up useless code in kvm_timer_enable	2016-11-15 11:54:16 +00:00
pmu.c	KVM: arm64: Require in-kernel irqchip for PMU support	2016-09-27 18:57:07 +02:00
trace.h