mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 23:08:42 +07:00
20fe6f98fa
Turning off a cluster when all 4 cores of the cluster are powered off saves power significantly. Powering off the A15 L2 alone gives around 100mW in savings. Add support for powering off the A15/A7 clusters on exynos5420/5800. The patch enables specific register bits which ensure that: - cluster L2 will be turned on before the first man is powered up. - last man will be turned off before the cluster L2 is turned off. - core is powered down before powering it up. Remove the exynos_cluster_power_control function completely as we can rely on the above mentioned bits rather than polling the cluster power status register. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
334 lines
16 KiB
C
334 lines
16 KiB
C
/*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Power management unit definition
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_PMU_H
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#define __ASM_ARCH_REGS_PMU_H __FILE__
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#include <mach/map.h>
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#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
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#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
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#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
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#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
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#define S5P_USE_STANDBY_WFI0 (1 << 16)
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#define S5P_USE_STANDBY_WFE0 (1 << 24)
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#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
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#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
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#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
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#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
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#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
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#define S5P_INFORM0 S5P_PMUREG(0x0800)
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#define S5P_INFORM1 S5P_PMUREG(0x0804)
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#define S5P_INFORM5 S5P_PMUREG(0x0814)
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#define S5P_INFORM6 S5P_PMUREG(0x0818)
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#define S5P_INFORM7 S5P_PMUREG(0x081C)
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#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
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#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
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#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
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#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
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#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
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#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
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#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
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#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
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#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
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#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
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#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
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#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
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#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
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#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
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#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
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#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
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#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
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#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
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#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
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#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
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#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
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#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
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#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
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#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
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#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
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#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
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#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
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#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
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#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
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#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
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#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
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#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
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#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
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#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
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#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
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#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
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#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
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#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
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#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
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#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
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#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
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#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
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#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
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#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
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#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
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#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
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#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
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#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
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#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
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#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
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#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
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#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
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#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
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#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
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#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
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#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
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#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
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#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
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#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
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#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
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#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
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#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
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#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
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#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
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#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
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#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
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#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
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#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
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(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
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#define EXYNOS_ARM_CORE_STATUS(_nr) \
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(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
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#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
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#define EXYNOS_COMMON_CONFIGURATION(_nr) \
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(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
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#define EXYNOS_COMMON_STATUS(_nr) \
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(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
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#define EXYNOS_COMMON_OPTION(_nr) \
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(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
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#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
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#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
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#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
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#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
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#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
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#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
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#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
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#define S5P_CORE_LOCAL_PWR_EN 0x3
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/* Only for EXYNOS4210 */
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#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
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#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
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#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
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#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
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#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
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#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
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/* Only for EXYNOS4x12 */
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#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
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#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
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#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
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#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
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#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
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#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
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#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
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#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
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#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
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#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
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#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
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#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
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#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
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#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
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#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
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#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
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#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
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#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
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#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
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#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
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#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
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#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
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#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
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#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
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#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
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#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
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#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
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#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
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#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
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#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
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#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
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#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
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#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
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#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
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#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
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#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
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#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
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#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
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/* Only for EXYNOS4412 */
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#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
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#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
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#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
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#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
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#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
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#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
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/* For EXYNOS5 */
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#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
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#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
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#define EXYNOS5_SYS_WDTRESET (1 << 20)
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#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
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#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
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#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
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#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
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#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
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#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
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#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
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#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
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#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
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#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
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#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
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#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
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#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
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#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
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#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
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#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
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#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
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#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
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#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
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#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
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#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
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#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
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#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
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#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
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#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
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#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
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#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
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#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
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#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
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#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
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#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
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#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
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#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
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#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
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#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
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#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
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#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
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#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
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#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
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#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
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#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
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#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
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#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
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#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
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#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
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#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
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#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
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#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
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#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
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#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
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#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
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#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
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#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
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#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
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#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
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#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
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#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
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#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
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#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
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#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
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#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
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#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
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#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
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#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
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#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
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#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
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#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
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#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
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#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
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#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
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#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
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#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
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#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
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#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
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#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
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#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
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#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
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#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
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#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
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#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
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#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
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#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
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#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
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#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
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#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
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#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
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#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
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#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
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#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
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#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
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#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
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#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
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#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
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#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
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#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
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#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
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#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
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#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
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#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
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#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
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#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
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#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
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#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
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#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
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#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
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#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
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#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
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#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
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#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
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#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
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#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
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#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
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#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
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#define EXYNOS5_USE_SC_COUNTER (1 << 0)
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#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
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#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
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#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
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#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
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#define EXYNOS5420_SWRESET_KFC_SEL 0x3
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#include <asm/cputype.h>
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#define MAX_CPUS_IN_CLUSTER 4
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static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
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{
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return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
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+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
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}
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#endif /* __ASM_ARCH_REGS_PMU_H */
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