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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fcdc653751
RISC-V has the concept of a cpu level interrupt controller. The interface for it is split between a standardized part that is exposed as bits in the mstatus/sstatus register and the mie/mip/sie/sip CRS. But the bit to actually trigger IPIs is not standardized and just mentioned as implementable using MMIO. Add support for IPIs using MMIO using the SiFive clint layout (which is also shared by Ariane, Kendryte and the Qemu virt platform). Additionally the MMIO block also supports the time value and timer compare registers, so they are also set up using the same OF node. Support for other layouts should also be relatively easy to add in the future. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: update include guard format; fix checkpatch issues; minor commit message cleanup] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_SBI_H
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#define _ASM_RISCV_SBI_H
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#include <linux/types.h>
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#ifdef CONFIG_RISCV_SBI
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#define SBI_SET_TIMER 0
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#define SBI_CONSOLE_PUTCHAR 1
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#define SBI_CONSOLE_GETCHAR 2
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#define SBI_CLEAR_IPI 3
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#define SBI_SEND_IPI 4
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#define SBI_REMOTE_FENCE_I 5
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#define SBI_REMOTE_SFENCE_VMA 6
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#define SBI_REMOTE_SFENCE_VMA_ASID 7
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#define SBI_SHUTDOWN 8
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#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
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register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
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register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
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register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
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register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
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register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
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asm volatile ("ecall" \
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: "+r" (a0) \
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: "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
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: "memory"); \
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a0; \
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})
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/* Lazy implementations until SBI is finalized */
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#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
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#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
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#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
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#define SBI_CALL_3(which, arg0, arg1, arg2) \
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SBI_CALL(which, arg0, arg1, arg2, 0)
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#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
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SBI_CALL(which, arg0, arg1, arg2, arg3)
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static inline void sbi_console_putchar(int ch)
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{
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SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
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}
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static inline int sbi_console_getchar(void)
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{
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return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
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}
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static inline void sbi_set_timer(uint64_t stime_value)
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{
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#if __riscv_xlen == 32
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SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
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#else
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SBI_CALL_1(SBI_SET_TIMER, stime_value);
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#endif
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}
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static inline void sbi_shutdown(void)
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{
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SBI_CALL_0(SBI_SHUTDOWN);
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}
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static inline void sbi_clear_ipi(void)
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{
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SBI_CALL_0(SBI_CLEAR_IPI);
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}
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static inline void sbi_send_ipi(const unsigned long *hart_mask)
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{
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SBI_CALL_1(SBI_SEND_IPI, hart_mask);
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}
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static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
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{
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SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
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}
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static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
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unsigned long start,
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unsigned long size)
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{
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SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
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}
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static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
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unsigned long start,
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unsigned long size,
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unsigned long asid)
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{
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SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
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}
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#else /* CONFIG_RISCV_SBI */
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/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
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void sbi_set_timer(uint64_t stime_value);
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void sbi_clear_ipi(void);
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void sbi_send_ipi(const unsigned long *hart_mask);
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void sbi_remote_fence_i(const unsigned long *hart_mask);
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#endif /* CONFIG_RISCV_SBI */
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#endif /* _ASM_RISCV_SBI_H */
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