Atish Patra 1d5c17e470 RISC-V: Typo fixes in image header and documentation. ... There are some typos in boot image header and riscv boot documentation. Fix the typos. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Link: https://lore.kernel.org/r/20191009010637.9955-1-atish.patra@wdc.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>		2019-12-19 09:32:45 -07:00
..
asm-offsets.h
asm-prototypes.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
asm.h	RISC-V: Clear load reservations while restoring hart contexts	2019-10-01 13:16:40 -07:00
atomic.h
barrier.h
bitops.h
bug.h	riscv: cleanup <asm/bug.h>	2019-10-23 14:53:46 -07:00
cache.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
cacheflush.h	riscv: fix build break after macro-to-function conversion in generic cacheflush.h	2019-07-18 08:16:56 -07:00
clint.h	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
cmpxchg.h
csr.h	riscv: clear the instruction cache and all registers when booting	2019-11-17 15:17:39 -08:00
current.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
delay.h
elf.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
fence.h
fixmap.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
ftrace.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
futex.h	Merge branch 'next/nommu' into for-next	2019-11-22 18:59:09 -08:00
hugetlb.h
hwcap.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
image.h	RISC-V: Typo fixes in image header and documentation.	2019-12-19 09:32:45 -07:00
io.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
irq.h	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
irqflags.h	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
Kbuild	asm-generic: Make msi.h a mandatory include/asm header	2019-11-26 13:14:11 -06:00
kprobes.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
linkage.h
mmio.h	generic ioremap support	2019-11-28 10:57:12 -08:00
mmiowb.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
mmu_context.h
mmu.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
module.h
page.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
pci.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
perf_event.h
pgalloc.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
pgtable-32.h
pgtable-64.h	RISC-V: Setup initial page tables in two stages	2019-07-09 09:08:04 -07:00
pgtable-bits.h
pgtable.h	generic ioremap support	2019-11-28 10:57:12 -08:00
processor.h	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
ptrace.h	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
sbi.h	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
seccomp.h	riscv: add support for SECCOMP and SECCOMP_FILTER	2019-10-29 11:32:10 -07:00
sifive_l2_cache.h
smp.h	riscv: cleanup riscv_cpuid_to_hartid_mask	2019-09-05 01:51:57 -07:00
sparsemem.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
spinlock_types.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
spinlock.h
string.h
switch_to.h	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
syscall.h
thread_info.h	riscv: add support for SECCOMP and SECCOMP_FILTER	2019-10-29 11:32:10 -07:00
timex.h	riscv: add support for MMIO access to the timer registers	2019-11-13 14:10:40 -08:00
tlb.h
tlbflush.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
uaccess.h	riscv: add nommu support	2019-11-17 15:17:39 -08:00
unistd.h
vdso.h
word-at-a-time.h