mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 18:38:46 +07:00
62e59c4e69
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
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static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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div = div ? 4 : 1;
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return parent_rate / div;
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}
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static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 mask;
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u8 parent = 0;
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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}
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return parent;
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}
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static struct clk_ops gateclk_ops = {
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.recalc_rate = socfpga_gate_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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static const struct clk_ops dbgclk_ops = {
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.recalc_rate = socfpga_dbg_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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struct clk *s10_register_gate(const char *name, const char *parent_name,
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const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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void __iomem *regbase, unsigned long gate_reg,
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unsigned long gate_idx, unsigned long div_reg,
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unsigned long div_offset, u8 div_width,
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unsigned long bypass_reg, u8 bypass_shift,
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u8 fixed_div)
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{
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struct clk *clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (!socfpga_clk)
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return NULL;
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socfpga_clk->hw.reg = regbase + gate_reg;
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socfpga_clk->hw.bit_idx = gate_idx;
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gateclk_ops.enable = clk_gate_ops.enable;
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gateclk_ops.disable = clk_gate_ops.disable;
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socfpga_clk->fixed_div = fixed_div;
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if (div_reg)
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socfpga_clk->div_reg = regbase + div_reg;
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else
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socfpga_clk->div_reg = NULL;
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socfpga_clk->width = div_width;
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socfpga_clk->shift = div_offset;
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if (bypass_reg)
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socfpga_clk->bypass_reg = regbase + bypass_reg;
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else
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socfpga_clk->bypass_reg = NULL;
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socfpga_clk->bypass_shift = bypass_shift;
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if (streq(name, "cs_pdbg_clk"))
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init.ops = &dbgclk_ops;
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else
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init.ops = &gateclk_ops;
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init.name = name;
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init.flags = flags;
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init.num_parents = num_parents;
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init.parent_names = parent_names ? parent_names : &parent_name;
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socfpga_clk->hw.hw.init = &init;
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clk = clk_register(NULL, &socfpga_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(socfpga_clk);
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return NULL;
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}
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return clk;
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}
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