mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:42:49 +07:00
c7ec75ea4d
Checking bypass_reg is incorrect for calculating the cnt_clk rates. Instead we should be checking that there is a proper hardware register that holds the clock divider. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|---|---|---|
| .. | ||
| clk-gate-a10.c | ||
| clk-gate-s10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph-s10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll-s10.c | ||
| clk-pll.c | ||
| clk-s10.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| stratix10-clk.h | ||