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0cf35df353
Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> |
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| .. | ||
| core.c | ||
| dispc.c | ||
| display.c | ||
| dpi.c | ||
| dsi.c | ||
| dss_features.c | ||
| dss_features.h | ||
| dss.c | ||
| dss.h | ||
| Kconfig | ||
| Makefile | ||
| manager.c | ||
| overlay.c | ||
| rfbi.c | ||
| sdi.c | ||
| venc.c | ||