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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 20:56:40 +07:00
OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver
enum dss_clock structure is replaced with generic names that could be used across OMAP2420, 2430, 3xxx, 44xx platforms. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
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872462cdfc
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6af9cd1431
@ -184,7 +184,7 @@ static int omap_dss_probe(struct platform_device *pdev)
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}
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/* keep clocks enabled to prevent context saves/restores during init */
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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r = rfbi_init_platform_driver();
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if (r) {
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@ -251,7 +251,7 @@ static int omap_dss_probe(struct platform_device *pdev)
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pdata->default_device = dssdev;
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}
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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return 0;
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@ -551,9 +551,9 @@ void dispc_restore_context(void)
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static inline void enable_clocks(bool enable)
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{
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if (enable)
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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else
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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}
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bool dispc_go_busy(enum omap_channel channel)
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@ -2311,7 +2311,7 @@ unsigned long dispc_fclk_rate(void)
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unsigned long r = 0;
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if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
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r = dss_clk_get_rate(DSS_CLK_FCK1);
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r = dss_clk_get_rate(DSS_CLK_FCK);
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else
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#ifdef CONFIG_OMAP2_DSS_DSI
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r = dsi_get_dsi1_pll_rate();
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@ -2439,7 +2439,7 @@ void dispc_dump_regs(struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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DUMPREG(DISPC_REVISION);
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DUMPREG(DISPC_SYSCONFIG);
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@ -2596,7 +2596,7 @@ void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_VID_PRELOAD(0));
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DUMPREG(DISPC_VID_PRELOAD(1));
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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#undef DUMPREG
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}
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@ -107,7 +107,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
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bool is_tft;
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int r = 0;
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
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dssdev->panel.acbi, dssdev->panel.acb);
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@ -137,7 +137,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
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dispc_set_lcd_timings(dssdev->manager->id, t);
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err0:
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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return r;
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}
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@ -173,14 +173,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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goto err1;
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}
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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r = dpi_basic_init(dssdev);
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if (r)
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goto err2;
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#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
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dss_clk_enable(DSS_CLK_FCK2);
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dss_clk_enable(DSS_CLK_SYSCK);
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r = dsi_pll_init(dssdev, 0, 1);
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if (r)
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goto err3;
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@ -199,10 +199,10 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
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dsi_pll_uninit();
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err3:
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dss_clk_disable(DSS_CLK_FCK2);
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dss_clk_disable(DSS_CLK_SYSCK);
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#endif
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err2:
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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if (cpu_is_omap34xx())
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regulator_disable(dpi.vdds_dsi_reg);
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err1:
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@ -219,10 +219,10 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
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#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
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dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dsi_pll_uninit();
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dss_clk_disable(DSS_CLK_FCK2);
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dss_clk_disable(DSS_CLK_SYSCK);
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#endif
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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if (cpu_is_omap34xx())
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regulator_disable(dpi.vdds_dsi_reg);
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@ -654,18 +654,18 @@ static void dsi_vc_disable_bta_irq(int channel)
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static inline void enable_clocks(bool enable)
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{
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if (enable)
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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else
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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}
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/* source clock for DSI PLL. this could also be PCLKFREE */
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static inline void dsi_enable_pll_clock(bool enable)
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{
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if (enable)
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dss_clk_enable(DSS_CLK_FCK2);
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dss_clk_enable(DSS_CLK_SYSCK);
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else
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dss_clk_disable(DSS_CLK_FCK2);
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dss_clk_disable(DSS_CLK_SYSCK);
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if (enable && dsi.pll_locked) {
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if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
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@ -741,7 +741,7 @@ static unsigned long dsi_fclk_rate(void)
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if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
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/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
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r = dss_clk_get_rate(DSS_CLK_FCK1);
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r = dss_clk_get_rate(DSS_CLK_FCK);
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} else {
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/* DSI FCLK source is DSI2_PLL_FCLK */
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r = dsi_get_dsi2_pll_rate();
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@ -821,7 +821,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
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return -EINVAL;
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if (cinfo->use_dss2_fck) {
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cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
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cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
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/* XXX it is unclear if highfreq should be used
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* with DSS2_FCK source also */
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cinfo->highfreq = 0;
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@ -867,7 +867,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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int match = 0;
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unsigned long dss_clk_fck2;
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dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
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dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
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if (req_pck == dsi.cache_req_pck &&
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dsi.cache_cinfo.clkin == dss_clk_fck2) {
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@ -1319,7 +1319,7 @@ void dsi_dump_regs(struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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DUMPREG(DSI_REVISION);
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DUMPREG(DSI_SYSCONFIG);
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@ -1391,7 +1391,7 @@ void dsi_dump_regs(struct seq_file *s)
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DUMPREG(DSI_PLL_CONFIGURATION1);
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DUMPREG(DSI_PLL_CONFIGURATION2);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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#undef DUMPREG
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}
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@ -227,7 +227,7 @@ void dss_dump_clocks(struct seq_file *s)
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unsigned long dpll4_ck_rate;
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unsigned long dpll4_m4_ck_rate;
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
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@ -240,21 +240,21 @@ void dss_dump_clocks(struct seq_file *s)
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seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK1));
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dss_clk_get_rate(DSS_CLK_FCK));
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else
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seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK1));
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dss_clk_get_rate(DSS_CLK_FCK));
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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}
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void dss_dump_regs(struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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DUMPREG(DSS_REVISION);
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DUMPREG(DSS_SYSCONFIG);
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@ -265,7 +265,7 @@ void dss_dump_regs(struct seq_file *s)
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DUMPREG(DSS_PLL_CONTROL);
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DUMPREG(DSS_SDI_STATUS);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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#undef DUMPREG
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}
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@ -350,7 +350,7 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
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int dss_get_clock_div(struct dss_clock_info *cinfo)
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{
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cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
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cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
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if (cpu_is_omap34xx()) {
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unsigned long prate;
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@ -391,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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prate = dss_get_dpll4_rate();
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fck = dss_clk_get_rate(DSS_CLK_FCK1);
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fck = dss_clk_get_rate(DSS_CLK_FCK);
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if (req_pck == dss.cache_req_pck &&
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((cpu_is_omap34xx() && prate == dss.cache_prate) ||
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dss.cache_dss_cinfo.fck == fck)) {
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@ -418,7 +418,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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if (cpu_is_omap24xx()) {
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struct dispc_clock_info cur_dispc;
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/* XXX can we change the clock on omap2? */
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fck = dss_clk_get_rate(DSS_CLK_FCK1);
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fck = dss_clk_get_rate(DSS_CLK_FCK);
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fck_div = 1;
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dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
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@ -701,7 +701,7 @@ static void save_all_ctx(void)
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{
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DSSDBG("save context\n");
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dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
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dss_save_context();
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dispc_save_context();
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@ -709,7 +709,7 @@ static void save_all_ctx(void)
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dsi_save_context();
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#endif
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dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
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}
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static void restore_all_ctx(void)
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@ -807,13 +807,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk)
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switch (clk) {
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case DSS_CLK_ICK:
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return clk_get_rate(dss.dss_ick);
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case DSS_CLK_FCK1:
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case DSS_CLK_FCK:
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return clk_get_rate(dss.dss1_fck);
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case DSS_CLK_FCK2:
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case DSS_CLK_SYSCK:
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return clk_get_rate(dss.dss2_fck);
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case DSS_CLK_54M:
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case DSS_CLK_TVFCK:
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return clk_get_rate(dss.dss_54m_fck);
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case DSS_CLK_96M:
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case DSS_CLK_VIDFCK:
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return clk_get_rate(dss.dss_96m_fck);
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}
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@ -827,13 +827,13 @@ static unsigned count_clk_bits(enum dss_clock clks)
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if (clks & DSS_CLK_ICK)
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++num_clks;
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if (clks & DSS_CLK_FCK1)
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if (clks & DSS_CLK_FCK)
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++num_clks;
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if (clks & DSS_CLK_FCK2)
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if (clks & DSS_CLK_SYSCK)
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++num_clks;
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if (clks & DSS_CLK_54M)
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if (clks & DSS_CLK_TVFCK)
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++num_clks;
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if (clks & DSS_CLK_96M)
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if (clks & DSS_CLK_VIDFCK)
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++num_clks;
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return num_clks;
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@ -845,13 +845,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks)
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if (clks & DSS_CLK_ICK)
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clk_enable(dss.dss_ick);
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if (clks & DSS_CLK_FCK1)
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if (clks & DSS_CLK_FCK)
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clk_enable(dss.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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if (clks & DSS_CLK_SYSCK)
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clk_enable(dss.dss2_fck);
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if (clks & DSS_CLK_54M)
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if (clks & DSS_CLK_TVFCK)
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clk_enable(dss.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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if (clks & DSS_CLK_VIDFCK)
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clk_enable(dss.dss_96m_fck);
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dss.num_clks_enabled += num_clks;
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@ -873,13 +873,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks)
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if (clks & DSS_CLK_ICK)
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clk_disable(dss.dss_ick);
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if (clks & DSS_CLK_FCK1)
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if (clks & DSS_CLK_FCK)
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clk_disable(dss.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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if (clks & DSS_CLK_SYSCK)
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clk_disable(dss.dss2_fck);
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if (clks & DSS_CLK_54M)
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if (clks & DSS_CLK_TVFCK)
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clk_disable(dss.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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if (clks & DSS_CLK_VIDFCK)
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clk_disable(dss.dss_96m_fck);
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dss.num_clks_enabled -= num_clks;
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@ -903,9 +903,9 @@ static void dss_clk_enable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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clks |= DSS_CLK_VIDFCK;
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dss_clk_enable_no_ctx(clks);
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}
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@ -913,9 +913,9 @@ static void dss_clk_disable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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clks |= DSS_CLK_VIDFCK;
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dss_clk_disable_no_ctx(clks);
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}
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|
||||
|
@ -112,11 +112,11 @@ enum omap_parallel_interface_mode {
|
||||
};
|
||||
|
||||
enum dss_clock {
|
||||
DSS_CLK_ICK = 1 << 0,
|
||||
DSS_CLK_FCK1 = 1 << 1,
|
||||
DSS_CLK_FCK2 = 1 << 2,
|
||||
DSS_CLK_54M = 1 << 3,
|
||||
DSS_CLK_96M = 1 << 4,
|
||||
DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */
|
||||
DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */
|
||||
DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */
|
||||
DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */
|
||||
DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
|
||||
};
|
||||
|
||||
enum dss_clk_source {
|
||||
|
@ -1394,7 +1394,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
|
||||
}
|
||||
|
||||
r = 0;
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
if (!dss_cache.irq_enabled) {
|
||||
u32 mask;
|
||||
|
||||
@ -1407,7 +1407,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
|
||||
dss_cache.irq_enabled = true;
|
||||
}
|
||||
configure_dispc();
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
|
||||
spin_unlock_irqrestore(&dss_cache.lock, flags);
|
||||
|
||||
|
@ -490,7 +490,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
|
||||
|
||||
ovl->manager = mgr;
|
||||
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
/* XXX: on manual update display, in auto update mode, a bug happens
|
||||
* here. When an overlay is first enabled on LCD, then it's disabled,
|
||||
* and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
|
||||
@ -499,7 +499,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
|
||||
* but I don't understand how or why. */
|
||||
msleep(40);
|
||||
dispc_set_channel_out(ovl->id, mgr->id);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -141,9 +141,9 @@ static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
|
||||
static void rfbi_enable_clocks(bool enable)
|
||||
{
|
||||
if (enable)
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
else
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
}
|
||||
|
||||
void omap_rfbi_write_command(const void *buf, u32 len)
|
||||
@ -496,7 +496,7 @@ unsigned long rfbi_get_max_tx_rate(void)
|
||||
};
|
||||
|
||||
l4_rate = rfbi.l4_khz / 1000;
|
||||
dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
|
||||
dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ftab); i++) {
|
||||
/* Use a window instead of an exact match, to account
|
||||
@ -921,7 +921,7 @@ void rfbi_dump_regs(struct seq_file *s)
|
||||
{
|
||||
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
|
||||
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
|
||||
DUMPREG(RFBI_REVISION);
|
||||
DUMPREG(RFBI_SYSCONFIG);
|
||||
@ -952,7 +952,7 @@ void rfbi_dump_regs(struct seq_file *s)
|
||||
DUMPREG(RFBI_VSYNC_WIDTH);
|
||||
DUMPREG(RFBI_HSYNC_WIDTH);
|
||||
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
#undef DUMPREG
|
||||
}
|
||||
|
||||
|
@ -70,7 +70,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
|
||||
/* In case of skip_init sdi_init has already enabled the clocks */
|
||||
if (!sdi.skip_init)
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
|
||||
sdi_basic_init(dssdev);
|
||||
|
||||
@ -130,7 +130,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
|
||||
|
||||
return 0;
|
||||
err2:
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
regulator_disable(sdi.vdds_sdi_reg);
|
||||
err1:
|
||||
omap_dss_stop_device(dssdev);
|
||||
@ -145,7 +145,7 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
|
||||
|
||||
dss_sdi_disable();
|
||||
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
|
||||
regulator_disable(sdi.vdds_sdi_reg);
|
||||
|
||||
@ -175,7 +175,7 @@ int sdi_init(bool skip_init)
|
||||
* of them until sdi_display_enable is called.
|
||||
*/
|
||||
if (skip_init)
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -391,11 +391,11 @@ static void venc_reset(void)
|
||||
static void venc_enable_clocks(int enable)
|
||||
{
|
||||
if (enable)
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
|
||||
DSS_CLK_96M);
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
|
||||
DSS_CLK_VIDFCK);
|
||||
else
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
|
||||
DSS_CLK_96M);
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
|
||||
DSS_CLK_VIDFCK);
|
||||
}
|
||||
|
||||
static const struct venc_config *venc_timings_to_config(
|
||||
|
Loading…
Reference in New Issue
Block a user