Yash Shah 087958a176 riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure ... Implement cache_get_priv_group() that will make use of a generic ops structure to return a private attribute group for custom cache info. Using riscv_set_cacheinfo_ops() users can hook their own custom function to return the private attribute group for cacheinfo. In future we can add more ops to this generic ops structure for SOC specific cacheinfo. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-05-20 15:05:05 -07:00
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asm-offsets.h
asm-prototypes.h
asm.h
atomic.h
barrier.h
bitops.h
bug.h	riscv: add macro to get instruction length	2020-03-26 09:24:49 -07:00
cache.h
cacheflush.h	riscv: Use flush_icache_mm for flush_icache_user_range	2020-03-03 10:28:10 -08:00
cacheinfo.h	riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure	2020-05-20 15:05:05 -07:00
clint.h	riscv: fix the IPI missing issue in nommu mode	2020-03-18 18:44:39 -07:00
cmpxchg.h
cpu_ops.h	RISC-V: Support cpu hotplug	2020-03-31 11:28:30 -07:00
csr.h	RISC-V: Remove N-extension related defines	2020-05-04 14:09:00 -07:00
current.h	RISC-V: Stop relying on GCC's register allocator's hueristics	2020-03-03 10:28:13 -08:00
delay.h
elf.h
fence.h
fixmap.h	riscv: introduce interfaces to patch kernel code	2020-03-26 09:24:52 -07:00
ftrace.h
futex.h	futex: arch_futex_atomic_op_inuser() calling conventions change	2020-03-27 23:58:51 -04:00
gdb_xml.h	riscv: Use the XML target descriptions to report 3 system registers	2020-05-18 11:38:11 -07:00
hugetlb.h
hwcap.h	RISC-V: Add bitmap reprensenting ISA features common across CPUs	2020-05-04 14:08:59 -07:00
image.h
io.h
irq.h
irqflags.h
kasan.h	riscv: Use macro definition instead of magic number	2020-03-26 09:29:53 -07:00
Kbuild	asm-generic: make more kernel-space headers mandatory	2020-04-02 09:35:25 -07:00
kdebug.h	riscv: Add KGDB support	2020-05-18 11:38:10 -07:00
kgdb.h	riscv: Use the XML target descriptions to report 3 system registers	2020-05-18 11:38:11 -07:00
kprobes.h
linkage.h
mmio.h	riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU	2020-05-12 17:20:32 -07:00
mmiowb.h	riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'	2020-05-13 17:11:46 -07:00
mmu_context.h
mmu.h
module.h	arch: split MODULE_ARCH_VERMAGIC definitions out to <asm/vermagic.h>	2020-04-23 10:50:26 +09:00
page.h	mm/vma: define a default value for VM_DATA_DEFAULT_FLAGS	2020-04-10 15:36:21 -07:00
parse_asm.h	riscv: Add SW single-step support for KDB	2020-05-18 11:38:12 -07:00
patch.h	riscv: Remove the 'riscv_' prefix of function name	2020-05-18 11:38:13 -07:00
pci.h
perf_event.h	riscv: perf: RISCV_BASE_PMU should be independent	2020-05-12 16:21:46 -07:00
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h
pgtable.h	riscv: pgtable: Fix __kernel_map_pages build error if NOMMU	2020-05-13 17:11:39 -07:00
processor.h
ptdump.h	riscv: Add support to dump the kernel page tables	2020-03-26 09:29:49 -07:00
ptrace.h
sbi.h	RISC-V: Add SBI HSM extension definitions	2020-03-31 11:26:05 -07:00
seccomp.h
set_memory.h	RISC-V: Remove unused code from STRICT_KERNEL_RWX	2020-05-05 17:02:14 -07:00
smp.h	RISC-V: Support cpu hotplug	2020-03-31 11:28:30 -07:00
soc.h	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
sparsemem.h
spinlock_types.h
spinlock.h
string.h
switch_to.h
syscall.h	riscv: fix seccomp reject syscall code path	2020-03-05 13:58:15 -08:00
thread_info.h
timex.h
tlb.h
tlbflush.h
uaccess.h	riscv: uaccess should be used in nommu mode	2020-03-18 18:44:30 -07:00
unistd.h
vdso.h
vermagic.h	arch: split MODULE_ARCH_VERMAGIC definitions out to <asm/vermagic.h>	2020-04-23 10:50:26 +09:00
vmalloc.h
word-at-a-time.h