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For most platforms, the CPU and ESAI device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the ESAI is in BE mode. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
56 lines
1.9 KiB
Plaintext
56 lines
1.9 KiB
Plaintext
Freescale Enhanced Serial Audio Interface (ESAI) Controller
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The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
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for serial communication with a variety of serial devices, including industry
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standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
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other DSPs. It has up to six transmitters and four receivers.
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Required properties:
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- compatible : Compatible list, must contain "fsl,imx35-esai".
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- clocks: Contains an entry for each entry in clock-names.
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- clock-names : Includes the following entries:
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"core" The core clock used to access registers
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"extal" The esai baud clock for esai controller used to derive
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HCK, SCK and FS.
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"fsys" The system clock derived from ahb clock used to derive
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HCK, SCK and FS.
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- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].
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- fsl,esai-synchronous: This is a boolean property. If present, indicating
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that ESAI would work in the synchronous mode, which means all the settings
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for Receiving would be duplicated from Transmition related registers.
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- big-endian : If this property is absent, the native endian mode will
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be in use as default, or the big endian mode will be in use for all the
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device registers.
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Example:
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esai: esai@02024000 {
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compatible = "fsl,imx35-esai";
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 0x04>;
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clocks = <&clks 208>, <&clks 118>, <&clks 208>;
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clock-names = "core", "extal", "fsys";
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dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <128>;
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fsl,esai-synchronous;
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big-endian;
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status = "disabled";
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};
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