The Pinctrl module (ioc) controls the Pad's function select
(each pad can have 8 functions), Pad's Drive Strength, Pad's
Pull Select and Pad's Input Disable status.
The ioc has two modules, ioc_top & ioc_rtc. Both of these two
modules have function select/clear, Pull select and Drive
Strength registers. But only ioc_rtc has input-disable
registers. The Pads on ioc_top have to access ioc_rtc to set
their input-disable status and intpu-disable-value.
So have to use one ioc driver instance to drive these two
ioc modules at the same time, and each ioc module will be
treat as one bank on the "IOC Device".
The GPIO Controller controls the GPIO status if the Pad has
been config as GPIO by Pinctrl already. Includes the GPIO
Input/output, Interrupt type, Interrupt Status, and Set/Get
Values.
The GPIO pull up/down are controlled by Pinctrl.
There are 7 GPIO Groups and splited into 3 MACROs in atlas7.
The GPIO Groups in one MACRO share one GPIO controllers, each
GPIO Group are treated as one GPIO bank.
For example:
In VDIFM macro, there is one GPIO Controller, it has 3 banks
to control 3 gpio groups. Its gpio name space is from 0 to 95.
The Device Tree can be written as following:
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>;
gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp";
bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp".
bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp".
bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp".
Signed-off-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This function is only referenced in this file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
MT8127 pinctrl/eint are similar to mt8135 and mt8173, add
support for mt8127 using mediatek common pinctrl driver.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add mt6397 support using mediatek common pinctrl driver.
mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip.
Pinctrl/GPIO driver should obtain regmap from PMIC,
so adding this support to common code.
Also, mt6397 is no need to support interrupt controller,
so changing common code to skip it.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Input enable and smt setting have different register,
modify code to fix it.
Several mediatek soc use similar input enable/smt setting
procedure as mt8173, some soc use generic input enable/smt
setting, some soc has no input enable/smt setting. Adding
common code to handle all those cases, so future soc driver
can use it.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Several mediatek soc use similar pull setting procedure as mt8173,
the pupd enable and resistance setting are in the same register.
Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set
in mt8173 to handle this case, so future soc driver can use it.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset
and mtk_pinctrl_devdata.chip_type are never used in code.
Remove them.
Some per-pin data are using int for pin number and offsets.
Change to short and rearrange to reduce const data size.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the required group function map and fill it at probe using
the pin capabilities information already present in the driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixed a small typo in the Cygnus GPIO driver
Signed-off-by: Jason Uy <jasonuy@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a driver for the pin controller present on the IMG Pistachio SoC.
This driver provides pinmux and pinconfig operations as well as GPIO
and IRQ chips for the GPIO banks.
Changes from v4:
- Switched to using gpiochip_add_pin_range().
- Fixed up Kconfig entry.
Changes from v3:
- Addressed review comments from Ezequiel.
Changes from v2:
- Removed module stuff which would be compiled out.
Changes from v1:
- Addressed review comments from Linus.
- Changed compatible string to "img,pistachio-system-pinctrl".
- Look for GPIO sub-nodes by name.
- A couple of bug fixes.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based
on the pin number. Create a common helper function that both
functions can use that also handles the case where no pin number is
found in the pins array.
This also fixes a small bug in pconf_get_pin where pconf_get_i2c0
would use the pins array index rather than the pin number.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As of commit 9d07d414d4 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic ARM
multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set,
and the check can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Regarding pin control, r8a7791 and r8a7793 are identical, so it is
sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The last serial port is called "SCIFB", not "SCIFAB".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller
Hub). It has slightly different pin configuration compared to the LP
version. This patch adds support for Sunrisepoint-H to the existing
pinctrl-sunrisepoint.c driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As of commit 9d07d414d4 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic DT-only ARM
multi-platform builds. The driver doesn't need to match platform
devices by name anymore, hence remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The old format to define pinctrl settings for imx in DT has two
hierarchy levels. The first level are function device nodes. The second
level are pingroups which contain a property fsl,pins. The original
intention was to define all pin functions in a single dtsi file and just
reference the correct ones in the board files.
This idea was rejected some time ago leading to the current design to
have all the pinfunctions defined in the board files. So we don't need
the function device nodes anymore.
This patch changes the pinctrl driver to accept devicetrees which do not
have the first hierarchy level, function device nodes. For example
karo-tx25 already has such a devicetree. Old devicetrees are still
parsed and supported.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.
This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:
pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};
mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}
conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};
conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};
conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};
conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Assign GPIO chip and irqchip to the GPIO container dynamically,
so we can set a unique name for each GPIO irqchip and see what
chip the hwirq offset actually relates to.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This activates strict mode muxing for the Nomadik pin controllers,
as these do not allow GPIO and functions to use the same pin
simultaneously.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
While the pinmux_ops are ideally just a vtable for pin mux
calls, the "strict" setting belongs so intuitively with the
pin multiplexing that we should move it here anyway. Putting
it in the top pinctrl_desc makes no sense.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Disallow simultaneous use of the the GPIO and peripheral mux
functions by setting a flag "strict" in struct pinctrl_desc.
The blackfin pinmux and gpio controller doesn't allow user to
set up a pin for both GPIO and peripheral function. So, add flag
strict in struct pinctrl_desc to check both gpio_owner and
mux_owner before approving the pin request.
v2-changes:
- if strict flag is set, check gpio_owner and mux_onwer in if and
else clause
v3-changes:
- add kerneldoc for this struct
- augment Documentation/pinctrl.txt
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.
Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the callback for set_multiple.
As this controller has a separate set and clear register, we
can't write directly to PIO_ODSR as this would required a cached
variable and would race with at91_gpio_set.
So build masks for the PIO_SODR and PIO_CODR registers and
write them together.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There was some mess in the dependencies in the pinctrl
Kconfig for compile tests under allmodconfig. Mea Culpa.
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
cycle:
New drivers:
- Intel Sunrisepoint
- AMD KERNCZ GPIO
- Broadcom Cygnus IOMUX
New subdrivers:
- Marvell MVEBU Armada 39x SoCs
- Samsung Exynos 5433
- nVidia Tegra 210
- Mediatek MT8135
- Mediatek MT8173
- AMLogic Meson8b
- Qualcomm PM8916
On top of this cleanups and development history for the above
drivers as issues were fixed after merging.
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Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pincontrol updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.1 development
cycle. Nothing really exciting this time: we basically added a few
new drivers and subdrivers and stabilized them in linux-next. Some
cleanups too. With sunrisepoint Intel has a real fine fully featured
pin control driver for contemporary hardware, and the AMD driver is
also for large deployments. Most of the others are ARM devices.
New drivers:
- Intel Sunrisepoint
- AMD KERNCZ GPIO
- Broadcom Cygnus IOMUX
New subdrivers:
- Marvell MVEBU Armada 39x SoCs
- Samsung Exynos 5433
- nVidia Tegra 210
- Mediatek MT8135
- Mediatek MT8173
- AMLogic Meson8b
- Qualcomm PM8916
On top of this cleanups and development history for the above drivers
as issues were fixed after merging"
* tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
pinctrl: sirf: move sgpio lock into state container
pinctrl: Add support for PM8916 GPIO's and MPP's
pinctrl: bcm2835: Fix support for threaded level triggered IRQs
sh-pfc: r8a7790: add EtherAVB pin groups
pinctrl: Document "function" + "pins" pinmux binding
pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
pinctrl: fsl: imx: Check for 0 config register
pinctrl: Add support for Meson8b
documentation: Extend pinctrl docs for Meson8b
pinctrl: Cleanup Meson8 driver
Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion.
pinctrl: at91: convert __raw to endian agnostic IO
pinctrl: constify of_device_id array
pinctrl: pinconf-generic: add dt node names to error messages
pinctrl: pinconf-generic: scan also referenced phandle node
pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
pinctrl: st: Display pin's function when printing pinctrl debug information
pinctrl: st: Show correct pin direction also in GPIO mode
pinctrl: st: Supply a GPIO get_direction() call-back
pinctrl: st: Move st_get_pio_control() further up the source file
...
Pull trivial tree from Jiri Kosina:
"Usual trivial tree updates. Nothing outstanding -- mostly printk()
and comment fixes and unused identifier removals"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
goldfish: goldfish_tty_probe() is not using 'i' any more
powerpc: Fix comment in smu.h
qla2xxx: Fix printks in ql_log message
lib: correct link to the original source for div64_u64
si2168, tda10071, m88ds3103: Fix firmware wording
usb: storage: Fix printk in isd200_log_config()
qla2xxx: Fix printk in qla25xx_setup_mode
init/main: fix reset_device comment
ipwireless: missing assignment
goldfish: remove unreachable line of code
coredump: Fix do_coredump() comment
stacktrace.h: remove duplicate declaration task_struct
smpboot.h: Remove unused function prototype
treewide: Fix typo in printk messages
treewide: Fix typo in printk messages
mod_devicetable: fix comment for match_flags
Instead of referring to a global static variable for the sgpio
locking, use the state container to contain the lock.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently, the driver uses handle_simple_irq for all IRQ types and hard
codes the acknowledge for different IRQ types into the handler. It is
better to use the IRQ core as intended and let it handle the differences
between the various types of IRQ. For example the current system does
not work for threaded level triggered IRQs as these need to be masked
until the threaded handler has run.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add EtherAVB pin groups to R8A7790 PFC driver.
Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).
The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardware that is
based on the same host controller design.
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
0 is used in all pinfunction definitions when a config register is not
available, for example imx25-pinfunc.h. If a configuration value is used
for such a pinfunction the driver will always write it to the
configuration register if it is not -1. For a 0 configuration register
the configuration value is written to offset 0x0. This can lead to a
crashing/hanging system without any warning message.
This patch checks for 0 config register and sets the internal value to
-1. If the configuration value is not NO_PADCTL this leads to an error
message that applying the configuration failed.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use endian agnostic _relaxed IO accessors instead of the __raw ones.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node
directly referenced by phandle, not only its child nodes.
The "parent scan" feature needs a few other changes:
* Move the pinconf_generic_dt_node_to_map() error handling code to a common
place, under the 'exit' label.
* Move the pins/groups strings count earlier in
pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when
these properties are missing or wrong
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds suspend/resume support to the Armada XP pinctrl
driver, by simply saving and restoring the MPP registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Great for easily determining which mode a pin is operating in.
This patch was particularly helpful when debugging a recent GPIO/
Pinctrl disparity issue.
Before:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
After [GPIO]:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
After [Alt]:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Until now ST's pinconf_dbg_show() call-back has displayed the PIO
alternate function direction, which is only relevant if a pin is
operating in an alternate function mode i.e not GPIO mode. If a
pin is in GPIO mode its direction is both set and status is
obtained by a completely different/unrelated bunch of registers.
This change ensures that the correct pin direction is shown, even
if a pin is operating in GPIO mode.
Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ST's hardware differentiates between GPIO mode and Pinctrl alternate
functions. When a pin is in GPIO mode, there are dedicated registers
to set and obtain direction status. However, If a pin's alternate
function is in use then the direction is set and status is derived
from a bunch of syscon registers. The issue is; until now there was
a lack of parity between the two.
For example:
Catting the two following information sources could result in
conflicting information (output has been snipped for simplicity):
$ cat /sys/kernel/debug/gpio
GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4:
gpio-33 (? ) out hi
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
In this example GPIO-33 is a GPIO controlled LED, which is set for
output, as you'd expect. However, when the same information is
drafted from Pinctrl, it clearly states that OE (Output Enable) is
not set i.e. the pin is set for input. This is because OE normally
only represents alternate functions and has no bearing on how the
pin operates when in Alt-0 (GPIO mode).
This patch changes the current semantics and provides a parity link
between the two subsystems. The get_direction() call-back firstly
determines which function a pin is operating in, then uses the
appropriate helpers for that mode.
Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
st_get_pio_control() will be used by subsequent calls which are
to be located above its original position. This is required to
prevent the need for an unnecessary forward-declaration/prototype.
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This call fetches the numerical function value a specified pin is
currently operating in. Function zero is more often than not the
GPIO function. Greater than zero values represent an alternative
function. You'd need to either look those up in the Device Tree
sources or the Programmer's Manual.
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Optional fields are set to -1 by various preprocessor macros. Make
sure the fields can actually store them.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Also make the table a bit compact.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Prefer devm_kcalloc over devm_kzalloc with multiply.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ARM64 maintainer doesn't want to add MACH_* for each SoC.
Adjust mt8173 pinctrl kconfig entry so user can manually select it.
Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove erroneous kfree for memory allocated by devm_kzalloc
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the following build failure:
In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0:
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error:
pinctrl-mtk-common.h: No such file or directory
seen when building arm:multi_v7_defconfig.
Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.")
Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On sun4i-a10, when GPIOs are configured as external interrupt the value for
them in the data register does not seem to get updated, so set their mux to
input (and restore afterwards) when reading the pin.
Missed edges seem to be buffered, so this does not introduce a race
condition.
I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to
be affected, the input value representation in the data register does seem
to correctly get updated to the actual pin value while in irq mode there.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The r8a7790 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The emev2 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently all PFC registers lie in low 32-bit address space. Hence use
u32 instead of unsigned long to store PFC register addresses in pinctrl
tables. All calculations of virtual addresses use a phys_addr_t
intermediate, so we know where to add an offset if the 32-bit assumption
ever becomes false.
While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a
64-bit shmobile_defconfig kernel.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All other loops over sh_pfc_soc_info.data_regs[] use
pinmux_data_reg.regwidth as the sentinel, which is safer as zero is
never a valid regwidth value (reg could be zero if we start using it to
store an offset).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As register and field widths and offsets are in the range 1..32, use
unsigned int (mostly replacing unsigned long) to store them in local
variables and for passing them around.
Move to one variable per line, move variables to the beginning of the
block where they are used, and drop superfluous initializations while we
are at it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.
This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs by 26460 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM.
Current driver patch only support GPIO in x86.
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
[Moved back to <linux/gpio.h> header]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The alive pin controller on exynos7 does not support external gpio
interrupts. Hence, remove the eint_gpio_init call-back for it. This
fixes the following error message seen during exynos7 boot-up:
"samsung-pinctrl 10580000.pinctrl: irq number not available"
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF configurations such as bias pull up/down, and
drive strength are also supported in this driver.
Pins from the ASIU GPIO controller can be individually muxed to GPIO
function, through interaction with the Cygnus IOMUX controller
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Due to pinconf_generic_parse_dt_config() API changes in pinctrl
devel branch, add one parameter to fix build error.
Also fix warning:
drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning:
too many arguments for format [-Wformat-extra-args]
dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret);
^
by removing extra parameter when calling dev_err in mtk_pctrl_init.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
MTK EINT does not support generating interrupt on both edges.
Emulate this by changing edge polarity while enable irq,
set types and interrupt handling. This follows an example of
drivers/gpio/gpio-mxc.c.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add mt8173 support using mediatek common pinctrl driver.
MT8173 have a different ies_smt setting register than mt8135,
so adding this support to common code.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
MTK SoC support external interrupt(EINT) from most SoC pins.
Add EINT support to pinctrl driver.
Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly
replacing unsigned long) to store (parts of) register values and masks.
Switch the shadow register operations from {set,clear}_bit() to plain C
bit operations, as the former can operate on long data only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 3dac1918a4 ("pinctrl: imx: detect uninitialized pins") needs
the values in struct imx_pin_reg to be -1. This has been done in a
rather unorthodox way by setting the memory to 0xff using memset...
Use a proper for loop to initialize the whole array with -1.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The gpiochip_lock_as_irq call can fail and return an error,
while the irq_startup is not expected to fail (returns an
unsigned int which is not checked by irq core code).
irq_request/release_resources functions have been created
to address this problem.
Move gpiochip_lock/unlock_as_irq calls into
irq_request/release_resources functions to prevent using a
gpio as an irq if the gpiochip_lock_as_irq call failed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
From the comments of gpiod_direction_output(), need to set @value
as initial output, so update the lowlevel routine to make it work.
Signed-off-by: jason.cj.chen<jason.cj.chen@intel.com>
Signed-off-by: qipeng.zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This enables support of 'input-enable' pinconf generic property in
the pinctrl driver.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This makes the pinctrl driver to use the generic pinconf
interface. Mainly it gives us a way to use debugfs to dump
group configurations.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is no code ender the 'err' label. Just return the error code directly.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra210's pinmux supports a different set of pins/options than earlier
SoCs, so requires its own driver (well, table of pin-specific data).
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular
pin's IO buffers are configured to accept "high voltage" input signals.
The TRM for different chips names the register field rcv-sel on older
SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl
driver so that DT files can use naming consistent with the TRM.
This new property name will be documented in the patch that adds support
for the new SoC.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some of the pinmux configuration bits that exist in "drive group"
registers in Tegra30..Tegra124 move to the "pinmux" registers on future
chips. Add a flag to support this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Various non-semantic tweaks and layout/consistency fixes for existing
Tegra pinctrl drivers.
Move the definition of DRV_PINGROUP_REG() before the definition of
PINGROUP() so that a future SoC driver can invoke the former from the
latter.
PINGROUP_BIT_Y(n) is just n, so replace it with n.
Re-wrap the parameters to *PINGROUP().
Keep various enums sorted in the Tegra124 driver.
Various white-space consistency fixes.
These changes aim to update existing drivers to be consistent with future
SoC drivers. While we could ignore these tweaks to the existing drivers,
I'd like to keep everything as consistent as possible for easy comparison.
Besides, I auto-generate the drivers, and maintaining special-cases to
keep the differences in place is annoying.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After the last user of the in_pd/in_pu bias parameters of the _PCRH()
macro was removed in commit 80da8e02d2 ("sh-pfc: r8a7740: Add bias
(pull-up/down) pinconf support"), bias parameters are supposed to be
configured using the generic pinctl mechanism, which calls the
.set_bias() method.
However, the PORTCR() macro still represents the control register as
consisting of two 4-bit fields. Hence the bias configuration in the
uppermost 2 bits is always overwritten with zeroes when a pin is
configured for GPIO, disabling any previously configured bias.
Use the variable config register macro instead, to represent the
register as having 4 fields, and to make sure only the input/output
control and function fields are touched.
This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile
AP4 (sh7372), and SH-Mobile AG5 (sh73a0).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The r8a7791 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The BIOS might reconfigure pins as it needs when S3 is entered. This might
cause drivers using the GPIOs to fail because the state was wrong or
interrupts stopped working.
Fix this by saving and restoring enough pin context over system sleep.
Reported-by: Hans Holmberg <hans.holmberg@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of handling everything in the driver's first level interrupt
handler, we can take advantage of already existing flow handlers that are
provided by the IRQ core.
This changes the functionality a bit also. Previously the driver looped
over pending interrupts in a single loop, restarting the loop if some
interrupt changed state. This caused problem with Lenovo Thinkpad 10
digitizer that it was not able to deassert the interrupt before the driver
disabled the interrupt for good (looplimit was exhausted).
Rework the interrupt handling logic a bit so that we provide proper mask,
ack and unmask operations in terms of Baytrail GPIO hardware and loop over
pending interrupts only once. If the interrupt remains asserted the first
level handler will be re-triggered automatically.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the pin is already configured as GPIO and it has any of the triggering
flags set, we may get spurious interrupts depending on the state of the
pin.
Prevent this by clearing the triggering flags on such pins. However, if the
pin is also configured as "direct IRQ" we leave the flags as is. Otherwise
it will prevent interrupts that are routed directly to IO-APIC.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a
GPIO pin and it is exposed to the operating system as Windows 8 button
array. This is implemented in Linux as a driver using gpio_keys.
However, BIOS on this particula machine forgot to mux the pin to be a GPIO
instead of native function, which results following message to be seen on
the console:
byt_gpio INT33FC:02: pin 16 cannot be used as GPIO.
This causes power button to not work as the driver was not able to request
the GPIO it needs.
So instead of completely preventing this we allow turning the pin as GPIO
but issue warning that something might be wrong.
Reported-by: Benjamin Adler <benadler@gmx.net>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Framework changes and enhancements:
- Passing -DDEBUG recursively to subdir drivers so we get
debug messages properly turned on.
- Infer map type from DT property in the groups parsing code
in the generic pinconfig code.
- Support for custom parameter passing in generic pin config.
This is used when you are using the generic pin config, but
want to add a few custom properties that no other driver
will use.
- New drivers:
- Driver for the Xilinx Zynq
- Driver for the AmLogic Meson SoCs
- New features in drivers:
- Sleep support (suspend/resume) for the Cherryview driver
- mvebeu a38x can now mux a UART on pins MPP19 and MPP20
- Migrated the qualcomm driver to generic pin config handling
of extended config options in the core code.
- Support BUS1 and AUDIO in the Exynos pin controller.
- Add some missing functions in the sun6i driver.
- Add support for the A31S variant in the sun6i driver.
- EMEv2 support in the Renesas PFC driver.
- Ass support for Qualcomm MSM8916 in the qcom driver.
- Deleted features
- Drop support for the SiRF Marco that was never released to
the market.
- Drop SH7372 support as the support for this platform is
removed from the kernel.
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Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pincontrol updates from Linus Walleij:
:This is the bulk of pin control changes for the v3.20 cycle:
Framework changes and enhancements:
- Passing -DDEBUG recursively to subdir drivers so we get debug
messages properly turned on.
- Infer map type from DT property in the groups parsing code in the
generic pinconfig code.
- Support for custom parameter passing in generic pin config. This
is used when you are using the generic pin config, but want to add
a few custom properties that no other driver will use.
New drivers:
- Driver for the Xilinx Zynq
- Driver for the AmLogic Meson SoCs
New features in drivers:
- Sleep support (suspend/resume) for the Cherryview driver
- mvebeu a38x can now mux a UART on pins MPP19 and MPP20
- Migrated the qualcomm driver to generic pin config handling of
extended config options in the core code.
- Support BUS1 and AUDIO in the Exynos pin controller.
- Add some missing functions in the sun6i driver.
- Add support for the A31S variant in the sun6i driver.
- EMEv2 support in the Renesas PFC driver.
- Add support for Qualcomm MSM8916 in the qcom driver.
Deleted features
- Drop support for the SiRF Marco that was never released to the
market.
- Drop SH7372 support as the support for this platform is removed
from the kernel"
* tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits)
sh-pfc: emev2 - Fix mangled author name
pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs
pinctrl: imx25: fix numbering for pins
pinctrl: pinctrl-imx: don't use invalid value of conf_reg
pinctrl: qcom: delete pin_config_get/set pinconf operations
pinctrl: qcom: Add msm8916 pinctrl driver
DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding
pinctrl: qcom: increase variable size for register offsets
pinctrl: hide PCONFDUMP in #ifdef
pinctrl: rockchip: Only mask interrupts; never disable
pinctrl: zynq: Fix usb0 pins
pinctrl: sh-pfc: sh7372: Remove DT binding documentation
pinctrl: sh-pfc: sh7372: Remove PFC support
sh-pfc: Add emev2 pinmux support
sh-pfc: add macro to define pinmux without function
pinctrl: add driver for Amlogic Meson SoCs
staging: drivers: pinctrl: Fixed checkpatch.pl warnings
pinctrl: exynos: Add AUDIO pin controller for exynos7
sh-pfc: r8a7790: add MLB+ pin group
sh-pfc: r8a7791: add MLB+ pin group
...
