Commit Graph

13 Commits

Author SHA1 Message Date
Chris Packham
90b9dc9694 ARM: dts: armada-xp: add label to sdram-controller node
Add the label "sdramc" to the sdram-controller nodes for the Armada-XP
and 98dx3236 SoCs.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-08 11:49:16 +02:00
Joshua Scott
8003136174 ARM: dts: armada-xp-98dx3236: Switch to armada-38x-uart serial node
Switch to the "marvell,armada-38x-uart" driver variant to empty
the UART buffer before writing to the UART_LCR register.

Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>.
Cc: stable@vger.kernel.org
Fixes: 43e28ba877 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236")
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-27 17:34:38 +02:00
Chris Packham
f2aeded4a6 ARM: dts: mvebu: add "marvell,prestera" to PP nodes
The compatible string "marvell,prestera" allows drivers to have code
common to any prestera variant.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-21 13:07:46 +02:00
Chris Packham
3e1ad82a19 ARM: dts: mvebu: 98dx3236: Rename nand controller node
Update the 98dx3236 SoC and dependent boards to use
"nand-controller" instead of "nand".

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-20 17:26:50 +02:00
Chris Packham
163043ab55 ARM: dts: armada-xp-98dx: Add NAND pinctrl information
Add pin control information for the NAND interface on the Armada
98DX3236 and variants.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-18 18:36:57 +02:00
Gregory CLEMENT
d816b3cc77 arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-27 15:09:29 +02:00
Rob Herring
28fbb9c539 ARM: dts: marvell: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-03 14:29:22 +02:00
Chris Packham
3bef2ac4bd ARM: dts: mvebu: disable the rtc on 98dx3236 SoC
There is no rtc for the 98dx3236 and derivative SoCs. Disable the rtc
node inherited from the armada-370-xp base.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17 08:16:45 +02:00
Chris Packham
23988bab04 ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236
The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port
0.1 MEM" range was errantly kept when creating a specific dts for the
SoC.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08 09:52:55 +01:00
Chris Packham
b4bcfccb2c ARM: dts: mvebu: Move mv98dx3236 clock bindings
Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.

Moving the binding to the DFX block enables support for different clock
strapping options in hardware.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08 09:52:54 +01:00
Chris Packham
43e28ba877 ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08 09:52:53 +01:00
Chris Packham
35a647f12c ARM: dts: armada-xp-98dx3236: combine dfx server nodes
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give some compatibility with the Marvell
supplied SDK.

As no upstream driver currently exists for this block and support for
this SoC is still quite fresh in the kernel it should not be necessary
to retain a backwards compatible binding.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-08 09:52:52 +01:00
Chris Packham
3f81df559f ARM: dts: mvebu: Add device tree for 98DX3236 SoCs
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.

[gregory.clement@free-electrons.com: fix topic]
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-31 14:45:03 +01:00