Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC.
This includes:
- Cortex-A57 and Cortex-A53 CPU cores
(incl. L2 caches and power state definitions),
- Power Management Unit,
- PSCI firmware,
- Pin Function Controller,
- Clock, Reset, System, and Interrupt Controllers,
- SCIF2 serial console,
- Product Register,
- ARM Architectured Timer,
and various placeholders to allow to use salvator-xs.dtsi.
Based on r8a7796.dtsi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-9-geert+renesas@glider.be
CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to
CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_ARCH_R8A77961.
Relax dependencies by handling both symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-8-geert+renesas@glider.be
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
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Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-arm64-dt-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122941.12342-3-geert+renesas@glider.be
Add power domain indices for the R-Car M3-W+ (R8A77961) SoC.
Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s
Manual (Jul. 31, 2019).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
Add CMM units to Renesas R-Car Gen3 SoC that support it, and reference them
from the Display Unit they are connected to.
Sort the 'vsps', 'renesas,cmm' and 'status' properties in the DU unit
consistently in all the involved DTS.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20191016085548.105703-8-jacopo+renesas@jmondi.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
and use pciec1 physical interface for SATA (as SATA and PCIE1 share
the same physical interface), therefore move pciec1 enabling away
from hihope-rzg2-ex.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds support for Advantech idk-1110wr LVDS panel.
The HiHope RZ/G2[MN] is advertised as compatible with panel
idk-1110wr from Advantech, however the panel isn't sold alongside
the board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1570029619-43238-10-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RZ/G2N board is pin compatible with RZ/G2M board. However on the SoC
side RZ/G2N uses DU3 where as RZ/G2M uses DU2 for the DPAD. In order to
reuse the common dtsi for both the boards, it is required to move du clock
properties from common dtsi to board specific dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1570029619-43238-2-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Hook up r8a774b1 DMAC nodes to the IPMMUs. In particular SYS-DMAC0
gets tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1.
Based on work for the r8a7796 by Magnus Damm.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569313375-53428-7-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch removes audio port node from SoC device tree and
fixes the below dtb warning
Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
Fixes: e2f04248fc ("arm64: dts: renesas: r8a774a1: Add audio support")
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1570200761-884-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Describe the dynamic power coefficient of A53 CPUs.
Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/1568364608-46548-2-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/1568364608-46548-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
