Commit Graph

104 Commits

Author SHA1 Message Date
Hans de Goede
678e75d3e5 ARM: dts: sunxi: Add de_be0 clk parent pll to simplefb node
Avoid the parent pll for the mod-clk for de_be0 getting disabled when non of
the other users are enabled (which can happen when none of i2c, spi and mmc
are in use).

Note for now we point directly to the parent rather then to the de_be0 mod-clk
as that is not modelled in our devicetree yet.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:20:12 +01:00
Hans de Goede
e53a8b2201 ARM: dts: sun6i: Add simplefb node
Add a simplefb template node for u-boot to further fill and activate.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:17:34 +01:00
Chen-Yu Tsai
74c947ab33 ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.
The apb2 clocks are actually the same as apb1 clocks on the other sunxi
platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk".

Update the dtsi to use the new unified apb1 clk.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:55 +01:00
Chen-Yu Tsai
f6c3b04608 ARM: sun6i: DT: Add PLL6 multiple outputs
PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:00:23 +01:00
Maxime Ripard
5186d83a29 ARM: sunxi: Fix GPLv2 wording
During the GPL to GPL/X11 licensing migration, the GPL notice introduced
mentionned the device trees as a library, which is not really accurate. It
began to spread by copy and paste. Fix all these library mentions to reflect
the file that it's actually just a file.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 16:53:01 +01:00
Chen-Yu Tsai
532425a7a7 ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller
The dma controller requires that the ahb1 bus clock be driven by pll6
for peripheral access to work. Previously this was done in the dma
controller driver, but was since removed as part of a series to unify
the ahb1_mux and ahb1 clock drivers, in

    14e0e28 dmaengine: sun6i: Remove obsolete clk muxing code

Unfortunately the rest of that series did not make it, leaving us with
broken dma on sun6i.

This patch reparents ahb1_mux to pll6 using the DT assigned-clocks
properties in the dma controller node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-08 15:56:36 +01:00
Arnd Bergmann
cd7555aeae Allwinner DT Additions for 3.18
Mostly:
   - A23 bringup ongoing
   - New boards: HSG H702, Merrii A20 Hummingbird
   - sun(4|5|7)i DMA support
   - DT relicensing to a dual GPL/X11 license
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Merge tag 'sunxi-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt

Pull "Allwinner DT Additions for 3.18" from Maxime Ripard:

Mostly:
  - A23 bringup ongoing
  - New boards: HSG H702, Merrii A20 Hummingbird
  - sun(4|5|7)i DMA support
  - DT relicensing to a dual GPL/X11 license

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'sunxi-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (30 commits)
  ARM: dts: sun8i: Add DMA controller node
  ARM: dts: sun5i: Add DT for HSG H702 tablet board
  ARM: dts: sunxi: Add fixed 5V regulator
  ARM: sun8i: Relicense the A23 DTSI under GPLv2/X11
  ARM: sun7i: Relicense the A20 DTSI under GPLv2/X11
  ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11
  ARM: sun7i: Add support for Olimex A20-OLinuXino-LIME
  ARM: dts: sun7i: Add Merrii A20 Hummingbird board
  ARM: dts: sun7i: Add uart3/4/5, i2c3 and spi2 pinmux
  ARM: dt: sunxi: Remove i2c controller clock-frequency that matches default
  ARM: dts: sun8i: Enable i2c controllers on ippo-q8h-v5
  ARM: dts: sun8i: Add i2c controller nodes
  ARM: dts: sun8i: Add pin-muxing info for the i2c controllers
  ARM: dts: sun8i: Enable mmc controller on ippo-q8h-v5
  ARM: dts: sun8i: Add mmc controller nodes
  ARM: dts: sun8i: Add pin-muxing info for the mmc controllers
  ARM: dts: sun8i: Add mmc clocks to the dtsi
  ARM: dts: sun8i: ippo-q8h: Add pinctrl properties for R_UART
  ARM: dts: sun8i: Add pin muxing option for R_UART
  ARM: dts: sun8i: Add pinmux set for uart0
  ...
2014-09-25 18:13:49 +02:00
Maxime Ripard
6c3ba72415 ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-07 17:49:48 +02:00
Chen-Yu Tsai
447a0470a7 ARM: dt: sunxi: Remove i2c controller clock-frequency that matches default
The clock-frequency values of the i2c controller nodes match the
defaults of the driver. Remove the properties to use the defaults,
and be consistent with sun8i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-08-18 19:51:50 +02:00
Chen-Yu Tsai
5e7004351a ARM: dts: sun6i: add rtc device node
Now that we have a driver for sun6i's rtc hardware, add a device node
for it so we can use it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-08-17 09:57:09 +02:00
Chen-Yu Tsai
495bccf391 ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes
dtc was giving warnings for missing #address-cells and #size-cells for
the new sun6i-a31-hummingbird.dts, which has a i2c-based rtc device.

This patch adds the properties for all i2c controller nodes for sun6i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-28 11:34:39 +02:00
Chen-Yu Tsai
e5073fde6b ARM: dts: sun6i: Add ethernet alias for GMAC
Alias GMAC as ethernet0 so U-boot can fill in the MAC address.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-18 22:36:54 +02:00
Chen-Yu Tsai
3dca65f8a6 ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node
The A31 has the same GMAC found on the A20 SoC, except it has
an extra reset control.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-18 22:36:49 +02:00
Chen-Yu Tsai
ed29861ae8 ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-18 22:36:29 +02:00
Chen-Yu Tsai
ee39a3e308 ARM: dts: sun6i: Add pin muxing options for GMAC
The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-18 22:35:56 +02:00
Chen-Yu Tsai
7d4ff96dd3 ARM: dts: sunxi: Add #interrupt-cells to pinctrl nodes
The pinctrl device is also an interrupt controller for external
interrupts. Add the missing #interrupt-cells property.

Also remove the unused #address-cells property.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-01 09:48:53 +02:00
Linus Torvalds
82e627eb5e Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next
Pull timer core updates from Thomas Gleixner:
 "This time you get nothing really exciting:
   - A huge update to the sh* clocksource drivers
   - Support for two more ARM SoCs
   - Removal of the deprecated setup_sched_clock() API
   - The usual pile of fixlets all over the place"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
  clocksource: Add Freescale FlexTimer Module (FTM) timer support
  ARM: dts: vf610: Add Freescale FlexTimer Module timer node.
  clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation
  clocksource: sh_tmu: Remove unnecessary OOM messages
  clocksource: sh_mtu2: Remove unnecessary OOM messages
  clocksource: sh_cmt: Remove unnecessary OOM messages
  clocksource: em_sti: Remove unnecessary OOM messages
  clocksource: dw_apb_timer_of: Do not trace read_sched_clock
  clocksource: Fix clocksource_mmio_readX_down
  clocksource: Fix type confusion for clocksource_mmio_readX_Y
  clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
  clocksource: qcom: Implement read_current_timer for udelay
  ntp: Make is_error_status() use its argument
  ntp: Convert simple_strtol to kstrtol
  timer_stats/doc: Fix /proc/timer_stats documentation
  sched_clock: Remove deprecated setup_sched_clock() API
  ARM: sun6i: a31: Add support for the High Speed Timers
  clocksource: sun5i: Add support for reset controller
  clocksource: efm32: use $vendor,$device scheme for compatible string
  KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform
  ...
2014-06-04 15:57:20 -07:00
Maxime Ripard
b294ebbc0d ARM: sun6i: Fix OHCI2 node name
The unit-address doesn't match the reg property. Since the reg property is
correct, change the unit-address accordingly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-22 10:44:22 +02:00
Maxime Ripard
ce78e353aa ARM: sun6i: Define the A31 CPUs enable-method
That will allow to use the CPU_METHOD_OF_DECLARE definition we did previously.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-17 18:42:15 +02:00
Boris BREZILLON
209394aed5 ARM: sunxi: dt: declare the r_pio pin controller for A31 SoC
The A31 SoC has a different pin controller for PL and PM banks.
Define this new controller in the device tree.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-15 10:38:00 +02:00
Boris BREZILLON
cc08f5e9c1 ARM: sunxi: dt: add PRCM clk and reset controller subdevices
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-15 10:33:06 +02:00
Maxime Ripard
ef964085e0 ARM: sun6i: dt: Add support for the USB controllers
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
2014-05-14 14:30:03 +02:00
Maxime Ripard
94a1cd14bf ARM: sun6i: Add the USB clocks to the DTSI
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
2014-05-14 14:30:00 +02:00
Hans de Goede
5b753f0e27 ARM: dts: sun6i: Add mmc controller nodes
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 22:58:06 -05:00
Hans de Goede
adc54c8584 ARM: dts: sun6i: Add mmc clocks
Add clk-nodes for the mmc clocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 22:53:16 -05:00
Hans de Goede
9797eb83c8 ARM: dts: sun6i: Add pin-muxing info for the mmc controllers
This adds  pin-muxing info for the mmc controller / port combinations which
are known to be used on actual boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-04-28 12:38:05 -07:00
Maxime Ripard
b5a10b7699 ARM: sun6i: Add ARM PMU in A31 DTSI
Enable the performance monitoring unit found in the A31 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
2014-04-28 09:11:35 -07:00
Maxime Ripard
d2d878c453 ARM: sun6i: dt: Add A31 DMA controller to DTSI
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-04-23 15:10:55 +02:00
Maxime Ripard
28240d27d6 ARM: sun6i: Sort the NMI node by physical address
The DT are supposed to be ordered by physical address. Move the NMI node where
it belongs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-04-23 15:10:41 +02:00
Maxime Ripard
8cffcb0ca3 ARM: sun6i: a31: Add support for the High Speed Timers
The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-22 13:56:50 +02:00
Hans de Goede
a42ea60359 ARM: sun6i: dt: Fixup prcm node name
The prcm lives at address 0x01f01400 as the reg entry in its node already
correctly indicates, rename the node to match this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-04-14 11:57:18 +02:00
Linus Torvalds
f83ccb9358 ARM: SoC: device tree changes
A large part of the arm-soc patches are nowadays DT changes, adding support
 for new SoCs, boards and devices without changing kernel source. The plan
 is still to move the devicetree files out of the kernel tree and reduce
 the amount of churn going on here, but we keep finding reasons to delay
 doing that.
 
 Changes are really all over the place, with little sticking out particularly.
 We have contributions from a total of 116 people in this branch.
 
 Unfortunately, the size of this branch also causes a significant number
 of conflicts at the moment, typically when subsystem maintainers merge
 patches that change the driver at the same time as the dts files. In
 most cases this could be avoided because the dts changes are supposed
 to be compatible in both ways, and we are asking everyone to send ARM
 dts changes through our tree only.
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Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "A large part of the arm-soc patches are nowadays DT changes, adding
  support for new SoCs, boards and devices without changing kernel
  source.  The plan is still to move the devicetree files out of the
  kernel tree and reduce the amount of churn going on here, but we keep
  finding reasons to delay doing that.

  Changes are really all over the place, with little sticking out
  particularly.  We have contributions from a total of 116 people in
  this branch.

  Unfortunately, the size of this branch also causes a significant
  number of conflicts at the moment, typically when subsystem
  maintainers merge patches that change the driver at the same time as
  the dts files.  In most cases this could be avoided because the dts
  changes are supposed to be compatible in both ways, and we are asking
  everyone to send ARM dts changes through our tree only"

* tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits)
  dts: stmmac: Document the clocks property in the stmmac base document
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  ARM: STi: stih41x: Add support for the FSM Serial Flash Controller
  ARM: STi: stih416: Add support for the FSM Serial Flash Controller
  ARM: tegra: fix Dalmore pinctrl configuration
  ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm
  ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND
  ARM: dts: Build all keystone dt blobs
  ARM: dts: keystone: Fix control register range for clktsip
  ARM: dts: keystone: Fix domain register range for clkfftc1
  ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot
  ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap
  ARM: dts: bcm21664: Add device tree files.
  ARM: DT: bcm21664: Device tree bindings
  ARM: efm32: properly namespace i2c location property
  ARM: efm32: fix unit address part in USART2 device nodes' names
  ARM: mvebu: Enable NAND controller in Armada 385-DB
  ARM: mvebu: Add support for NAND controller in Armada 38x SoC
  ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs
  ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs
  ...
2014-04-05 15:29:04 -07:00
Linus Torvalds
683b6c6f82 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq code updates from Thomas Gleixner:
 "The irq department proudly presents:

   - Another tree wide sweep of irq infrastructure abuse.  Clear winner
     of the trainwreck engineering contest was:
         #include "../../../kernel/irq/settings.h"

   - Tree wide update of irq_set_affinity() callbacks which miss a cpu
     online check when picking a single cpu out of the affinity mask.

   - Tree wide consolidation of interrupt statistics.

   - Updates to the threaded interrupt infrastructure to allow explicit
     wakeup of the interrupt thread and a variant of synchronize_irq()
     which synchronizes only the hard interrupt handler.  Both are
     needed to replace the homebrewn thread handling in the mmc/sdhci
     code.

   - New irq chip callbacks to allow proper support for GPIO based irqs.
     The GPIO based interrupts need to request/release GPIO resources
     from request/free_irq.

   - A few new ARM interrupt chips.  No revolutionary new hardware, just
     differently wreckaged variations of the scheme.

   - Small improvments, cleanups and updates all over the place"

I was hoping that that trainwreck engineering contest was a April Fools'
joke.  But no.

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (68 commits)
  irqchip: sun7i/sun6i: Disable NMI before registering the handler
  ARM: sun7i/sun6i: dts: Fix IRQ number for sun6i NMI controller
  ARM: sun7i/sun6i: irqchip: Update the documentation
  ARM: sun7i/sun6i: dts: Add NMI irqchip support
  ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
  genirq: Export symbol no_action()
  arm: omap: Fix typo in ams-delta-fiq.c
  m68k: atari: Fix the last kernel_stat.h fallout
  irqchip: sun4i: Simplify sun4i_irq_ack
  irqchip: sun4i: Use handle_fasteoi_irq for all interrupts
  genirq: procfs: Make smp_affinity values go+r
  softirq: Add linux/irq.h to make it compile again
  m68k: amiga: Add linux/irq.h to make it compile again
  irqchip: sun4i: Don't ack IRQs > 0, fix acking of IRQ 0
  irqchip: sun4i: Fix a comment about mask register initialization
  irqchip: sun4i: Fix irq 0 not working
  genirq: Add a new IRQCHIP_EOI_THREADED flag
  genirq: Document IRQCHIP_ONESHOT_SAFE flag
  ARM: sunxi: dt: Convert to the new irq controller compatibles
  irqchip: sunxi: Change compatibles
  ...
2014-04-01 11:22:57 -07:00
Hans de Goede
536a44d427 ARM: sun7i/sun6i: dts: Fix IRQ number for sun6i NMI controller
The IRQ line used in sun6i-a31.dtsi for the NMI controller is wrong.
This causes a IRQ storm since the NMI controller is repeatedly fired.
This patch fixes this problem assigning the correct IRQ number to the
NMI controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-31 11:12:57 +02:00
Carlo Caione
8ff973a267 ARM: sun7i/sun6i: dts: Add NMI irqchip support
This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Acked-by: maxime.ripard@free-electrons.com
Link: http://lkml.kernel.org/r/1395256879-8475-3-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-26 01:00:50 +01:00
Maxime Ripard
ca5d04d908 ARM: sunxi: dt: Update the watchdog compatibles
The watchdog compatibles were following a different pattern than the one found
in the other devices. Now that the driver supports the right pattern, switch to
it in the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-13 11:28:34 +01:00
Maxime Ripard
b4f26440d9 ARM: sunxi: dt: Convert to the new clocksource compatible
Switch the device tree to the new compatibles introduced in the timer driver
to have a common pattern accross all Allwinner SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-03-11 23:04:50 +01:00
Maxime Ripard
8be188b84b ARM: sun6i: Enable the I2C muxing options
The i2c controllers have a few muxing options on the A31. Enable the
ones found in the A31 Colombus board.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-07 15:28:06 +01:00
Maxime Ripard
96c7cc9b1a ARM: sun6i: Enable the I2C controllers
The A31 has 4 I2C controllers that are the same than the one in the
other Allwinner SoCs, except for the fact that they are asserted in
reset by the reset unit.

Add these i2c controllers to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-07 15:28:03 +01:00
Maxime Ripard
225b02163c ARM: sun6i: dt: Fix mod0 compatible
The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-28 12:04:53 +01:00
Maxime Ripard
bf6534a180 ARM: sunxi: dt: Convert to the new clock compatibles
Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-18 16:53:37 +01:00
Chen-Yu Tsai
7b5b2909f3 ARM: dts: sun6i: rename clock node names to clk@N
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-07 20:24:09 +01:00
Maxime Ripard
0d6efe339e ARM: sun6i: dt: Add SPI controllers to the A31 DTSI
The A31 has 4 SPI controllers. Add them in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-07 20:22:52 +01:00
Maxime Ripard
b0a09c756b ARM: sun6i: dt: Add PLL6 and SPI module clocks
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-07 20:22:49 +01:00
Maxime Ripard
54428d4025 ARM: sun6i: Add missing serial aliases
Some UART aliases have been defined, but not all of them. Add the remaining
ones to be consistent and to ease the parsing of the DT by the bootloaders.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-02-03 13:45:22 +01:00
Linus Torvalds
9b6d351a75 ARM: SoC DT updates for 3.14
DT and DT-conversion-related changes for various ARM platforms. Most
 of these are to enable various devices on various boards, etc, and not
 necessarily worth enumerating.
 
 New boards and systems continue to come in as new devicetree files that
 don't require corresponding C changes any more, which is indicating that
 the system is starting to work fairly well.
 
 A few things worth pointing out:
 
 * ST Ericsson ux500 platforms have made the major push to move over to fully
   support the platform with DT.
 * Renesas platforms continue their conversion over from legacy platform devices
   to DT-based for hardware description.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Olof Johansson:
 "DT and DT-conversion-related changes for various ARM platforms.  Most
  of these are to enable various devices on various boards, etc, and not
  necessarily worth enumerating.

  New boards and systems continue to come in as new devicetree files
  that don't require corresponding C changes any more, which is
  indicating that the system is starting to work fairly well.

  A few things worth pointing out:

   * ST Ericsson ux500 platforms have made the major push to move over
     to fully support the platform with DT
   * Renesas platforms continue their conversion over from legacy
     platform devices to DT-based for hardware description"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
  ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
  ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
  ARM: dts: sirf: add lost minigpsrtc device node
  ARM: dts: sirf: add clock, frequence-voltage table for CPU0
  ARM: dts: sirf: add lost bus_width, clock and status for sdhci
  ARM: dts: sirf: add lost clocks for cphifbg
  ARM: dts: socfpga: add pl330 clock
  ARM: dts: socfpga: update L2 tag and data latency
  arm: sun7i: cubietruck: Enable the i2c controllers
  ARM: dts: add support for EXYNOS4412 based TINY4412 board
  ARM: dts: Add initial support for Arndale Octa board
  ARM: bcm2835: add USB controller to device tree
  ARM: dts: MSM8974: Add MMIO architected timer node
  ARM: dts: MSM8974: Add restart node
  ARM: dts: sun7i: external clock outputs
  ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
  ARM: dts: sun7i: Add pin muxing options for clock outputs
  ARM: dts: sun7i: Add rtp controller node
  ARM: dts: sun5i: Add rtp controller node
  ARM: dts: sun4i: Add rtp controller node
  ...
2014-01-23 18:45:38 -08:00
Maxime Ripard
81ee429ffd ARM: sun6i: dt: Add IP needed to bring up the additional cores
Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-16 21:15:12 +01:00
Maxime Ripard
6f97dc8d46 ARM: sun6i: dt: Fix interrupt trigger types
The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org # 3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-11 17:15:24 -08:00
Maxime Ripard
24a661e994 ARM: sun6i: Add the reset controller to the DTSI
The A31 has a reset controller IP that maintains a few other IPs in
reset, among which we can find the UARTs, high speed timers or the I2C.
Now that we have support for them, add the reset controllers to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-11-22 21:36:56 +01:00
Maxime Ripard
439d9f5801 ARM: sun6i: Fix the APB2 clock gates register size
The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-05 15:36:10 +02:00
Maxime Ripard
98096560eb ARM: sun6i: Enable clock support in the DTSI
Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-26 10:51:18 +02:00
Maxime Ripard
ab4238cd05 ARM: sun6i: Add UART0 muxing options
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard
140e1721d1 ARM: sunxi: dt: Add PIO controller to A31 DTSI
The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard
8aed3b3158 ARM: sunxi: Add Allwinner A31 DTSI
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a
PowerVR GPU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-16 23:18:22 +02:00