Commit Graph

935705 Commits

Author SHA1 Message Date
Lorenzo Bianconi
ea4906c4be mt76: mt7615: wake device before accessing regmap in debugfs
Make sure the device is in full-power before reading regs in debugfs

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
adfd5112c8 mt76: mt7615: introduce mt7615_mutex_{acquire,release} utilities
Introduce mt7615_mutex_{acquire,release} utility routines in order to
switch in full-power/low-power before/after accessing device register-map

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
08523a2a1d mt76: mt7615: add mt7615_pm_wake utility routine
Introduce mt7615_pm_wake utility routine to wake the device from
runtime low-power state (lower-power state is currently supported by
offload firmware for pcie devices).

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
a86f1d01f5 mt76: move mt76 workqueue in common code
Move mt76 workqueue from usb to common code in order to be reused adding
low-power support for mt7663 chipset

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
757b0e7fd6 mt76: mt7615: avoid polling in fw_own for mt7663
According to the vendor sdk, mt7663 does not need to poll register after
firmware own. Since just mt7622 polls status register, set proper
timeout value according to the vendor sdk

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Ryder Lee
0d4b690998 mt76: mt7915: avoid memcpy in rxv operation
Avoid memcpy in Rx hot path to slightly improve performance.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
05b5a339a7 mt76: mt76x2u: enable HC-M7662BU1
Enable support for HC-M7662BU1 module on mt76x2u driver

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Lorenzo Bianconi
40ba9a938f mt76: mt76x2: fix pci suspend/resume on mt7612e
Fix the following mt7612e hw hangs during suspend/resume reported on
Dell Vostro 3360

mt76x2e 0000:01:00.0: MCU message 2 (seq 11) timed out
mt76x2e 0000:01:00.0: MCU message 30 (seq 12) timed out
mt76x2e 0000:01:00.0: MCU message 30 (seq 13) timed out
mt76x2e 0000:01:00.0: Firmware Version: 0.0.00
mt76x2e 0000:01:00.0: Build: 1
mt76x2e 0000:01:00.0: Build Time: 201507311614____
mt76x2e 0000:01:00.0: Firmware running!
ieee80211 phy0: Hardware restart was requested
mt76x2e 0000:01:00.0: MCU message 2 (seq 1) timed out
mt76x2e 0000:01:00.0: MCU message 30 (seq 2) timed out
mt76x2e 0000:01:00.0: MCU message 30 (seq 3) timed out
mt76x2e 0000:01:00.0: Firmware Version: 0.0.00
mt76x2e 0000:01:00.0: Build: 1
mt76x2e 0000:01:00.0: Build Time: 201507311614____
mt76x2e 0000:01:00.0: Firmware running!
ieee80211 phy0: Hardware restart was requested
mt76x2e 0000:01:00.0: MCU message 31 (seq 5) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 6) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 7) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 8) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 9) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 10) timed out
mt76x2e 0000:01:00.0: MCU message 31 (seq 11) timed out
mt76x2e 0000:01:00.0: Firmware Version: 0.0.00
mt76x2e 0000:01:00.0: Build: 1
mt76x2e 0000:01:00.0: Build Time: 201507311614____
mt76x2e 0000:01:00.0: Firmware running!
ieee80211 phy0: Hardware restart was requested
------------[ cut here ]-----------
CPU: 3 PID: 11956 Comm: kworker/3:1 Not tainted 5.7.0-pf2 #1
Hardware name: Dell Inc.          Vostro 3360/0F5DWF, BIOS A18 09/25/2013
Workqueue: events_freezable ieee80211_restart_work [mac80211]
RIP: 0010:ieee80211_reconfig+0x234/0x1700 [mac80211]
RSP: 0018:ffffb803c23ffdf0 EFLAGS: 00010286
RAX: 00000000fffffff0 RBX: ffff9595a7564900 RCX: 0000000000000008
RDX: 0000000000000000 RSI: 0000000000000100 RDI: 0000000000000100
RBP: ffff9595a7ec07e0 R08: 0000000000000000 R09: 0000000000000001
R10: 0000000000000001 R11: 0000000000000000 R12: ffff9595a7ec18d0
R13: 00000000ffffffff R14: 0000000000000000 R15: 00000000fffffff0
FS:  0000000000000000(0000) GS:ffff9595af2c0000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 000055e56d7de000 CR3: 000000042200a001 CR4: 00000000001706e0
Call Trace:
 ieee80211_restart_work+0xb7/0xe0 [mac80211]
 process_one_work+0x1d4/0x3c0
 worker_thread+0x228/0x470
 ? process_one_work+0x3c0/0x3c0
 kthread+0x19c/0x1c0
 ? __kthread_init_worker+0x30/0x30
 ret_from_fork+0x35/0x40
wlp1s0:  Failed check-sdata-in-driver check, flags: 0x0
CPU: 3 PID: 11956 Comm: kworker/3:1 Tainted: G        W         5.7.0-pf2 #1
Hardware name: Dell Inc.          Vostro 3360/0F5DWF, BIOS A18 09/25/2013
Workqueue: events_freezable ieee80211_restart_work [mac80211]
RIP: 0010:drv_remove_interface+0x11f/0x130 [mac80211]
RSP: 0018:ffffb803c23ffc80 EFLAGS: 00010282
RAX: 0000000000000000 RBX: ffff9595a7564900 RCX: 0000000000000000
RDX: 0000000000000001 RSI: 0000000000000082 RDI: 00000000ffffffff
RBP: ffff9595a7ec1930 R08: 00000000000004b6 R09: 0000000000000001
R10: 0000000000000001 R11: 0000000000006f08 R12: ffff9595a7ec1000
R13: ffff9595a75654b8 R14: ffff9595a7ec0ca0 R15: ffff9595a7ec07e0
FS:  0000000000000000(0000) GS:ffff9595af2c0000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 000055e56d7de000 CR3: 000000042200a001 CR4: 00000000001706e0
Call Trace:
 ieee80211_do_stop+0x5af/0x8c0 [mac80211]
 ieee80211_stop+0x16/0x20 [mac80211]
 __dev_close_many+0xaa/0x120
 dev_close_many+0xa1/0x2b0
 dev_close+0x6d/0x90
 cfg80211_shutdown_all_interfaces+0x71/0xd0 [cfg80211]
 ieee80211_reconfig+0xa2/0x1700 [mac80211]
 ieee80211_restart_work+0xb7/0xe0 [mac80211]
 process_one_work+0x1d4/0x3c0
 worker_thread+0x228/0x470
 ? process_one_work+0x3c0/0x3c0
 kthread+0x19c/0x1c0
 ? __kthread_init_worker+0x30/0x30
 ret_from_fork+0x35/0x40

Fixes: 7bc04215a6 ("mt76: add driver code for MT76x2e")
Tested-by: Oleksandr Natalenko <oleksandr@redhat.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Ryder Lee
d9ea74c413 mt76: mt7915: update HE capabilities
Sync from SDK to update HE capabilities.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Felix Fietkau
4f0bce1c88 mt76: mt7615: implement testmode support
Supports sending a configurable number of packets with a specific rate
and configurable tx power levels / antenna settings, as well as displaying
rx statistics.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:16 +02:00
Felix Fietkau
f0efa86215 mt76: add API for testmode support
This can be used for calibration in the manufacturing process.
It supports sending a configurable number of packets with a specific rate
and configurable tx power levels / antenna settings.
It also supports receiving packets and showing some statistics, including
packet counters and detailed RSSI information.
It will only be compiled in if CONFIG_NL80211_TESTMODE is enabled

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Felix Fietkau
beffe070b1 mt76: vif_mask to struct mt76_phy
All drivers use this in pretty much the same way. Moving it to core helps with
some checks for the upcoming testmode support

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Felix Fietkau
b8c978663e mt76: mt7615: use full on-chip memory address for WF_PHY registers
Now that the bus access functions can use mapping for accessing full
register addresses, use it for WF_PHY registers to keep them constant.
Needed for follow-up work on testmode support

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Felix Fietkau
dc80405868 mt76: mt7615: add support for accessing RF registers via MCU
Includes debugfs files for testing it.
Will be used for testmode support.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Felix Fietkau
557b5a1747 mt76: mt7615: add support for accessing mapped registers via bus ops
Makes it possible to read/write them via debugfs, similar to mt7603

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Felix Fietkau
5bb923c767 mt76: mt7615: schedule tx tasklet and sta poll on mac tx free
Unlike on earlier chips, DMA completion on MT7615 does not imply actually
having sent out any packets.
Since AQL will prevent filling the hardware queues and will only allow more
packets to be passed to the driver after tx completion, it makes much more
sense to schedule the tx tasklet there.
This is also needed for scheduling tx in testmode support

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Lorenzo Bianconi
6ed942af4f mt76: mt76x2e: rename routines in pci.c
Rely on mt76x2e prefix in mt76x2/pci.c and align to the rest of
mt76 code

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Ryder Lee
dc076af55b mt76: mt7915: overwrite qid for non-bufferable mgmt frames
Overwrite hw queue id for non-bufferable management frames if the hw/fw
support always txq (altxq) in order to be in sync with mac txwi code

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Ryder Lee
80c9934004 mt76: mt7915: use ieee80211_tx_queue_params to avoid open coded
This is easy to add MU EDCA parameters in the future. This patch
also fixes a wrong cw_min assignment.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Ryder Lee
f68e6a1f85 mt76: mt7915: add MU-MIMO support
Enable MU-MIMO DL/UL and add relative counters in debugfs.

Currently MU modules read WTBL first to notify BA changes to
other cross modules, so adjust mt7915_mcu_sta_ba() accordingly.

Tested-by: Evelyn Tsai <evelyn.tsai@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Ryder Lee
dcdecb128b mt76: mt7915: add a fixed AC queue mapping
In MT7915, hardware queue map is flexible. However, certain firmware modules
like MU and U-APSD presume a fixed queue order to adapt some devices that have
DMA scheduler with a strict order, so this patch can help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Ryder Lee
b876658b5e mt76: mt7615: add .set_tsf callback
It is useful for IBSS Mesh to adjust t_clockdrift.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Lorenzo Bianconi
b807b368c4 mt76: add U-APSD support on AP side
Introduce U-APSD support in mt76 driver for AP interface

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:15 +02:00
Lorenzo Bianconi
4a58d5d109 mt76: rely on register macros
For consistency with the rest of the code always rely on defined
macros for register access

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Markus Theil
e39da597e5 mt76: fix include in pci.h
kernel test robot <lkp@intel.com> found the following issue
and Kalle Valo forwarded it to Linux wireless.

drivers/net/wireless/mediatek/mt76/pci.c:8:6:
warning: no previous prototype for 'mt76_pci_disable_aspm'

Fix this by adding the missing include of mt76.h as Kalle
suggested.

Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Markus Theil
9da82fb76d mt76: allow more channels, allowed in ETSI domain
While looking at the ETSI regulatory domain definitions
and a patch, which allows more channels for ath10k, I also
checked the channels allowed for mt76.

ETSI regulations would possibly allow to add channels 32, 68,
96, 144, 169 and 173. IEEE 802.11-2016 defines no operating class
for channels 32, 68 and 96. This leaves us channels 144, 169 and 173,
which are included in this patch.

I tested 169 and 173 with a mt76 based USB dongle (AVM AC 860) and they
worked fine. If I saw that right, these channels are also covered by
register definitions inside the driver.

Channel 144 should also work, but gets disabled by the kernel as of now.

Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Sean Wang
642023d043 mt76: mt7615: fix up typo in Kconfig for MT7663U
Fix up typo in Kconfig with indicating MT7663U is an 802.11ac device

Fixes: eb99cc95c3 ("mt76: mt7615: introduce mt7663u support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Sean Wang
73741b9bee mt76: mt7663: introduce ARP filter offload
Introduce ARP filter offload

Co-developed-by: Wan-Feng Jiang <Wan-Feng.Jiang@mediatek.com>
Signed-off-by: Wan-Feng Jiang <Wan-Feng.Jiang@mediatek.com>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Lorenzo Bianconi
be49c5356f mt76: usb: rely on mt76_for_each_q_rx
Rely on mt76_for_each_q_rx whenever possible in order to simply the code

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Felix Fietkau
a28bef561a mt76: mt7615: re-enable offloading of sequence number assignment
Preparation for supporting more offload features

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Lorenzo Bianconi
d3c8299852 mt76: overwrite qid for non-bufferable mgmt frames
Overwrite hw queue id for non-bufferable management frames if the hw
support always txq (altxq) in order to be in sync with mac txwi code

Fixes: cdad487405 ("mt76: mt7615: add dma and tx queue initialization for MT7622")
Fixes: f40ac0f3d3 ("mt76: mt7615: introduce mt7663e support")
Suggested-by: Felix Fietkau <nbd@nbd.name>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Lorenzo Bianconi
1fec635bcc mt76: mt7615: fix hw queue mapping
mt7622/mt7663 chipsets rely on a fixed reverse queue map order respect
to mac80211 one:
- q(0): IEEE80211_AC_BK
- q(1): IEEE80211_AC_BE
- q(2): IEEE80211_AC_VI
- q(3): IEEE80211_AC_VO

Fixes: cdad487405 ("mt76: mt7615: add dma and tx queue initialization for MT7622")
Fixes: f40ac0f3d3 ("mt76: mt7615: introduce mt7663e support")
Co-developed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Co-developed-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Lorenzo Bianconi
8fc49625a3 mt76: mt7615: fix lmac queue debugsfs entry
acs and wmm index are swapped in mt7615_queues_acq respect to the hw
design

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Lorenzo Bianconi
2cb002e3c2 mt76: add missing lock configuring coverage class
Coverage class callback can potentially run in parallel with other
routines (e.g. mt7615_set_channel) that configures timing registers.
Run coverage class callback holding mt76 mutex

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21 19:01:14 +02:00
Vladimir Oltean
71d4364abd net: dsa: use the ETH_MIN_MTU and ETH_DATA_LEN default values
Now that DSA supports MTU configuration, undo the effects of commit
8b1efc0f83 ("net: remove MTU limits on a few ether_setup callers") and
let DSA interfaces use the default min_mtu and max_mtu specified by
ether_setup(). This is more important for min_mtu: since DSA is
Ethernet, the minimum MTU is the same as of any other Ethernet
interface, and definitely not zero. For the max_mtu, we have a callback
through which drivers can override that, if they want to.

Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:35:04 -07:00
Jonathan McDowell
f58d2598cf net: dsa: qca8k: implement the port MTU callbacks
This switch has a single max frame size configuration register, so we
track the requested MTU for each port and apply the largest.

v2:
- Address review feedback from Vladimir Oltean

Signed-off-by: Jonathan McDowell <noodles@earth.li>
Acked-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:34:16 -07:00
Wang Hai
2b96692bcf net: hsr: remove redundant null check
Because kfree_skb already checked NULL skb parameter,
so the additional checks are unnecessary, just remove them.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wang Hai <wanghai38@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:33:32 -07:00
Christophe JAILLET
405e30e23c net/fealnx: switch from 'pci_' to 'dma_' API
The wrappers in include/linux/pci-dma-compat.h should go away.

The patch has been generated with the coccinelle script below and has been
hand modified to replace GFP_ with a correct flag.
It has been compile tested.

When memory is allocated, GFP_KERNEL can be used because it is called from
the probe function (i.e. 'fealnx_init_one()') and no lock is taken.

@@
@@
-    PCI_DMA_BIDIRECTIONAL
+    DMA_BIDIRECTIONAL

@@
@@
-    PCI_DMA_TODEVICE
+    DMA_TO_DEVICE

@@
@@
-    PCI_DMA_FROMDEVICE
+    DMA_FROM_DEVICE

@@
@@
-    PCI_DMA_NONE
+    DMA_NONE

@@
expression e1, e2, e3;
@@
-    pci_alloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&e1->dev, e2, e3, GFP_)

@@
expression e1, e2, e3;
@@
-    pci_zalloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&e1->dev, e2, e3, GFP_)

@@
expression e1, e2, e3, e4;
@@
-    pci_free_consistent(e1, e2, e3, e4)
+    dma_free_coherent(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_single(e1, e2, e3, e4)
+    dma_map_single(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_single(e1, e2, e3, e4)
+    dma_unmap_single(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4, e5;
@@
-    pci_map_page(e1, e2, e3, e4, e5)
+    dma_map_page(&e1->dev, e2, e3, e4, e5)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_page(e1, e2, e3, e4)
+    dma_unmap_page(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_sg(e1, e2, e3, e4)
+    dma_map_sg(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_sg(e1, e2, e3, e4)
+    dma_unmap_sg(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+    dma_sync_single_for_cpu(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_device(e1, e2, e3, e4)
+    dma_sync_single_for_device(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+    dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+    dma_sync_sg_for_device(&e1->dev, e2, e3, e4)

@@
expression e1, e2;
@@
-    pci_dma_mapping_error(e1, e2)
+    dma_mapping_error(&e1->dev, e2)

@@
expression e1, e2;
@@
-    pci_set_dma_mask(e1, e2)
+    dma_set_mask(&e1->dev, e2)

@@
expression e1, e2;
@@
-    pci_set_consistent_dma_mask(e1, e2)
+    dma_set_coherent_mask(&e1->dev, e2)

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:32:49 -07:00
Christophe JAILLET
e85da794f6 mISDN: switch from 'pci_' to 'dma_' API
The wrappers in include/linux/pci-dma-compat.h should go away.

The patch has been generated with the coccinelle script below and has been
hand modified to replace GFP_ with a correct flag.
It has been compile tested.

When memory is allocated in 'setup_hw()' (hfcpci.c) GFP_KERNEL can be used
because it is called from the probe function and no lock is taken.
The call chain is:
   hfc_probe()
   --> setup_card()
   --> setup_hw()

When memory is allocated in 'inittiger()' (netjet.c) GFP_ATOMIC must be
used because a spin_lock is taken by the caller (i.e. 'nj_init_card()')
This is also consistent with the other allocations done in the function.

@@
@@
-    PCI_DMA_BIDIRECTIONAL
+    DMA_BIDIRECTIONAL

@@
@@
-    PCI_DMA_TODEVICE
+    DMA_TO_DEVICE

@@
@@
-    PCI_DMA_FROMDEVICE
+    DMA_FROM_DEVICE

@@
@@
-    PCI_DMA_NONE
+    DMA_NONE

@@
expression e1, e2, e3;
@@
-    pci_alloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&e1->dev, e2, e3, GFP_)

@@
expression e1, e2, e3;
@@
-    pci_zalloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&e1->dev, e2, e3, GFP_)

@@
expression e1, e2, e3, e4;
@@
-    pci_free_consistent(e1, e2, e3, e4)
+    dma_free_coherent(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_single(e1, e2, e3, e4)
+    dma_map_single(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_single(e1, e2, e3, e4)
+    dma_unmap_single(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4, e5;
@@
-    pci_map_page(e1, e2, e3, e4, e5)
+    dma_map_page(&e1->dev, e2, e3, e4, e5)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_page(e1, e2, e3, e4)
+    dma_unmap_page(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_sg(e1, e2, e3, e4)
+    dma_map_sg(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_sg(e1, e2, e3, e4)
+    dma_unmap_sg(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+    dma_sync_single_for_cpu(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_device(e1, e2, e3, e4)
+    dma_sync_single_for_device(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+    dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+    dma_sync_sg_for_device(&e1->dev, e2, e3, e4)

@@
expression e1, e2;
@@
-    pci_dma_mapping_error(e1, e2)
+    dma_mapping_error(&e1->dev, e2)

@@
expression e1, e2;
@@
-    pci_set_dma_mask(e1, e2)
+    dma_set_mask(&e1->dev, e2)

@@
expression e1, e2;
@@
-    pci_set_consistent_dma_mask(e1, e2)
+    dma_set_coherent_mask(&e1->dev, e2)

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:32:14 -07:00
Briana Oursler
2b9843fbe1 tc-testing: Add tdc to kselftests
Add tdc to existing kselftest infrastructure so that it can be run with
existing kselftests. TDC now generates objects in objdir/kselftest
without cluttering main objdir, leaves source directory clean, and
installs correctly in kselftest_install, properly adding itself to
run_kselftest.sh script.

Add tc-testing as a target of selftests/Makefile. Create tdc.sh to run
tdc.py targets with correct arguments. To support single target from
selftest/Makefile, combine tc-testing/bpf/Makefile and
tc-testing/Makefile. Move action.c up a directory to tc-testing/.

Tested with:
 make O=/tmp/{objdir} TARGETS="tc-testing" kselftest
 cd /tmp/{objdir}
 cd kselftest
 cd tc-testing
 ./tdc.sh

 make -C tools/testing/selftests/ TARGETS=tc-testing run_tests

 make TARGETS="tc-testing" kselftest
 cd tools/testing/selftests
 ./kselftest_install.sh /tmp/exampledir
 My VM doesn't run all the kselftests so I commented out all except my
 target and net/pmtu.sh then:
 cd /tmp/exampledir && ./run_kselftest.sh

Co-developed-by: Davide Caratti <dcaratti@redhat.com>
Signed-off-by: Davide Caratti <dcaratti@redhat.com>
Signed-off-by: Briana Oursler <briana.oursler@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:29:37 -07:00
Vinay Kumar Yadav
c3466a768e crypto/chtls: Enable tcp window scaling option
Enable tcp window scaling option in hw based on sysctl settings
and option in connection request.

v1->v2:
- Set window scale option based on option in connection request.

Signed-off-by: Vinay Kumar Yadav <vinay.yadav@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:29:01 -07:00
David S. Miller
4f1b4da541 Merge branch 'net-atlantic-various-features'
Mark Starovoytov says:

====================
net: atlantic: various features

This patchset adds more features for Atlantic NICs:
 * media detect;
 * additional per-queue stats;
 * PTP stats;
 * ipv6 support for TCP LSO and UDP GSO;
 * 64-bit operations;
 * A0 ntuple filters;
 * MAC temperature (hwmon).

This work is a joint effort of Marvell developers.

v3:
 * reworked patches related to stats:
   . fixed u64_stats_update_* usage;
   . use simple assignment in _get_stats / _fill_stats_data;
   . made _get_sw_stats / _fill_stats_data return count as return value;
   . split rx and tx per-queue stats;

v2: https://patchwork.ozlabs.org/cover/1329652/
 * removed media detect feature (will be reworked and submitted later);
 * removed irq counter from stats;
 * use u64_stats_update_* to protect 64-bit stats;
 * use io-64-nonatomic-lo-hi.h for readq/writeq fallbacks;

v1: https://patchwork.ozlabs.org/cover/1327894/
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:39 -07:00
Mark Starovoytov
8dcf2ad39f net: atlantic: add hwmon getter for MAC temperature
This patch adds the possibility to obtain MAC temperature via hwmon.
On A1 there are two separate temperature sensors.
On A2 there's only one temperature sensor, which is used for reporting
both MAC and PHY temperature.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:39 -07:00
Dmitry Bogdanov
a89df867ce net: atlantic: A0 ntuple filters
This patch adds support for ntuple filters on A0.

Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Nikita Danilov
b98ffe6fa4 net: atlantic: use intermediate variable to improve readability a bit
This patch syncs up hw_atl_a0.c with an out-of-tree driver, where an
intermediate variable was introduced in a couple of functions to
improve the code readability a bit.

Signed-off-by: Nikita Danilov <ndanilov@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Mark Starovoytov
88bc9cf143 net: atlantic: use U32_MAX in aq_hw_utils.c
This patch replaces magic constant ~0U usage with U32_MAX in aq_hw_utils.c

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Pavel Belous
1e41b3fee7 net: atlantic: add support for 64-bit reads/writes
This patch adds support for 64-bit reads/writes where applicable, e.g.
A2 supports them.

Signed-off-by: Pavel Belous <pbelous@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Igor Russkikh
8bd6071085 net: atlantic: enable ipv6 support for TCP LSO and UDP GSO
This patch enables ipv6 support for TCP LSO and UDP GSO.
The code itself (aq_nic_map_skb) was ready for this after udp gso feature,
but corresponding NETIF_F_TSO6 wasn't enabled.

We now have tested both tcp and udp v6 GSO, and enabling them safely.

Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Pavel Belous
14b539a349 net: atlantic: PTP statistics
This patch adds PTP rings statistics. Before that
these were missing from overall stats, hardening debugging
and analysis.

Signed-off-by: Pavel Belous <pbelous@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00
Dmitry Bogdanov
aa7e17a3e3 net: atlantic: additional per-queue stats
This patch adds additional per-queue stats, these could
be useful for debugging and diagnostics.

Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com>
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20 18:07:38 -07:00