Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add a gate clock for controlling all clocks of Security Sub System
(SSS).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
As usual, this is the massive branch we have for each release. Lots of
various updates and additions of hardware descriptions on existing hardware,
as well as the usual additions of new boards and SoCs.
This is also the first release where we've started mixing 64- and 32-bit
DT updates in one branch.
(Specific details on what's actually here and new is pretty easy to tell
from the diffstat, so there's little point in duplicating listing it here.)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As usual, this is the massive branch we have for each release. Lots
of various updates and additions of hardware descriptions on existing
hardware, as well as the usual additions of new boards and SoCs.
This is also the first release where we've started mixing 64- and
32-bit DT updates in one branch.
(Specific details on what's actually here and new is pretty easy to
tell from the diffstat, so there's little point in duplicating listing
it here)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
ARM: dts: uniphier: add system-bus-controller nodes
ARM64: juno: disable NOR flash node by default
ARM: dts: uniphier: add outer cache controller nodes
arm64: defconfig: Enable PCI generic host bridge by default
arm64: Juno: Add support for the PCIe host bridge on Juno R1
Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
dts/ls2080a: Update Simulator DTS to add support of various peripherals
dts/ls2080a: Remove text about writing to Free Software Foundation
dts/ls2080a: Update DTSI to add support of various peripherals
doc: DTS: Update DWC3 binding to provide reference to generic bindings
doc/bindings: Update GPIO devicetree binding documentation for LS2080A
Documentation/dts: Move FSL board-specific bindings out of /powerpc
Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
arm64: Rename FSL LS2085A SoC support code to LS2080A
arm64: Use generic Layerscape SoC family naming
ARM: dts: uniphier: add ProXstream2 Vodka board support
ARM: dts: uniphier: add ProXstream2 Gentil board support
...
Merging in the few patches I had kept separate from main next/dt, since others
got merged here directly.
* next/arm64:
arm64: defconfig: Enable PCI generic host bridge by default
arm64: Juno: Add support for the PCIe host bridge on Juno R1
Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
arm64: dts: mt8173: Add clocks for SCPSYS unit
arm64: dts: mt8173: Add subsystem clock controller device nodes
+ Linux 4.3-rc5
When the DISP1 power domain is powered off, there's two clocks that need
to be temporarily reparented to OSC, and back to their original parents
when the domain is powered on again.
We expose these two clocks in the DT bindings so that the DT node of the
power domain can reference them.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
incorrectly used as a bit numbers. Fix it.
Tested on Exynos4210 based Origen board and on Exynos5250 based
Arndale board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Fixes: ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
FSYS0 fixed clocks are not added to fsys0_cmu_info, this makes
some of the usb clocks orphans. This fixes the same.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIS clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_CCORE clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_TOP1 clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_TOP0 clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This adds some of the missing GATE clocks of CMU_TOPC block.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Corrects the CMU_TOPC block clock names as per user manual.
This does not change any functionalities.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch corrects it.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks order.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This is a collection of a few late fixes and other misc. stuff that
had dependencies on things being merged from other trees.
The bulk of the changes are for samsung/exynos SoCs for some changes
that needed a few minor reworks so ended up a bit late. The others
are mainly for qcom SoCs: a couple fixes and some DTS updates.
There's one conflict with drivers/cpufreq/exynos-cpufreq.c because
it's now been completely removed, but there were some fixes that hit
mainline in the meantime.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM SoC updates from Kevin Hilman:
"This is a collection of a few late fixes and other misc stuff that had
dependencies on things being merged from other trees.
The bulk of the changes are for samsung/exynos SoCs for some changes
that needed a few minor reworks so ended up a bit late. The others
are mainly for qcom SoCs: a couple fixes and some DTS updates"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: multi_v7_defconfig: Enable PBIAS regulator
soc: qcom: smd: Correct fBLOCKREADINTR handling
soc: qcom: smd: Use correct remote processor ID
soc: qcom: smem: Fix errant private access
ARM: dts: qcom: msm8974-sony-xperia-honami: Use stdout-path
ARM: dts: qcom: msm8960-cdp: Use stdout-path
ARM: dts: qcom: msm8660-surf: Use stdout-path
ARM: dts: qcom: ipq8064-ap148: Use stdout-path
ARM: dts: qcom: apq8084-mtp: Use stdout-path
ARM: dts: qcom: apq8084-ifc6540: Use stdout-path
ARM: dts: qcom: apq8074-dragonboard: Use stdout-path
ARM: dts: qcom: apq8064-ifc6410: Use stdout-path
ARM: dts: qcom: apq8064-cm-qs600: Use stdout-path
ARM: dts: qcom: Label serial nodes for aliasing and stdout-path
reset: ath79: Fix missing spin_lock_init
reset: Add (devm_)reset_control_get stub functions
ARM: EXYNOS: switch to using generic cpufreq driver for exynos4x12
cpufreq: exynos: Remove unselectable rule for arm-exynos-cpufreq.o
ARM: dts: add iommu property to JPEG device for exynos4
ARM: dts: enable SPI1 for exynos4412-odroidu3
...
Commit d5e136a21b ("clk: samsung: Register
clk provider only after registering its all clocks", merged to v3.17-rc1)
modified a way that driver registers registers to core framework. This
change has not been applied to s5pv210 clocks driver, which has been
merged in parallel to that commit. This patch adds a missing call to
samsung_clk_of_add_provider(), so the driver is operational again.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: stable@vger.kernel.org # v3.17+
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by Thomas Abraham.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
ERROR: could not get clock /adc@126C0000:adc(0)
exynos-adc 126c0000.adc: failed getting clock, err = -2
exynos-adc: probe of 126c0000.adc failed with error -2
Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.
The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: <stable@vger.kernel.org>
Fixes: c63c574330 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch add CPU clock configuration data and instantiate the CPU
clock type for Exynos3250 to support Samsung specific cpu-clock type.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[b.zolnierkie: split exynos5250 support from the original patch]
[b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c]
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are
using it. The clkdev.h header isn't always used either, so remove
it and add in slab.h where files were relying on it to include
slab for them.
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.
Changes by Bartlomiej:
- fixed issue with wrong dividers being setup by Common Clock Framework
(by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board), this
was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
"[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
clock flags") but using these flags is not sufficient to fix the issue
observed
- removed Exynos5250 and Exynos5420 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Changes by Bartlomiej:
- fixed issue with setting lower dividers before the parent clock speed
was lowered (the issue resulted in lockup on Exynos4210 SoC based
Origen board when "ondemand" cpufreq governor was stress tested)
- fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
problem by moving cfg_data search outside of the spin locked area
- removed leftover kfree() in exynos_register_cpu_clock() that could
result in dereferencing the NULL pointer on error
- moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
- added missing "last chance" checks to wait_until_divider_stable() and
wait_until_mux_stable() (needed in case that IRQ handling took long
time to proceed and resulted in function printing incorrect error
message about timeout)
- moved E4210_CPU_DIV[0,1]() macros just before their only users,
this resulted in moving them from patch #2 to patch #3/6 ("clk:
samsung: exynos4: add cpu clock configuration data and instantiate
cpu clock")
- removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
macros for now
- added my Copyrights to drivers/clk/samsung/clk-cpu.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for
operation of secure monitor call (smc). System will hang when it executes 'smc'
with one of those clock is gated. All related clocks must be enabled.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent
clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic
Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to
'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR
of the MALI device.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
[cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This DIV_CPIF register must be stored when the system is suspended, and must
be restored on system resume. This patch adds the register to the list of
restored registers.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57}
core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to
change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver.
- 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM.
- 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Since commit 2893c37946 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/samsung/clk-exynos5260.c:138:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:328:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:392:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:494:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:583:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:644:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:779:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:898:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:962:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:1018:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:1165:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:1373:40: warning: Using plain integer as NULL pointer
drivers/clk/samsung/clk-exynos5260.c:1829:40: warning: Using plain integer as NULL pointer
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Staticize symbols not exported and not used outside of file.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add missing static to local (file-scope only) symbols.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Commit ae43b32891 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12") added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this in turn makes its parent clock aclk266_g2d to
be gated. But the clock needs to be ungated prior suspend to allow the
system to be suspend and resumed correctly.
Add GATE_BUS_TOP register to the list of registers to be restored when
the system enters into a suspend state so aclk266_g2d will be ungated.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
Cc: stable@vger.kernel.org # 3.19+
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch fixes the wrong parent clock of sclk_apollo clock
from 'div_apollo_pll' to 'div_apollo2'.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
CLK_PCLK_MONOTONIC_CNT clock had a wrong register assigned to it.
The correct register is ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch removes the CONFIG_ARCH_EXYNOS5433 and then use only the
CONFIG_ARCH_EXYNOS for ARM-64bit Exynos5433 SoC.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Commit 42773b28e7 ("clk: samsung: exynos4: Enable ARMCLK
down feature") enabled ARMCLK down feature on all Exynos4
SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature
causes a lockup when ondemand cpufreq governor is used.
Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs.
This patch was tested on:
- Exynos4210 SoC based Trats board
- Exynos4210 SoC based Origen board
- Exynos4412 SoC based Trats2 board
- Exynos4412 SoC based Odroid-U3 board
Cc: Daniel Drake <drake@endlessm.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Fixes: 42773b28e7 ("clk: samsung: exynos4: Enable ARMCLK down feature")
Cc: <stable@vger.kernel.org> # v3.17+
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
The statement
static const char *name[];
defines a modifiable array of pointers to constant chars. That is
*name[0] = 'f';
is forbidden, but
name[0] = "f";
is not. So marking an array that is defined as above with __initconst is
wrong. Either an additional const must be added such that the whole
definition reads:
static const char *const name[] __initconst;
or where this is not possible __initdata must be used.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Add clock controller for CMU ISP clock domain on Exynos3250,
providing clocks for FIMC-IS subsystem.
[b.michalska: use samsung_cmu_register_one to register
the provider; updated DT binding documentation]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Beata Michalska <b.michalska@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
[s.nawrocki: added __init attribute which was missing in function
exynos3250_cmu_platform_init() in function, which has been]
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This patch add CLKOUT driver support for Exynos3250 SoC.
Exynos3250 SoC PMU_DEBUG is the same with Exynos4's PMU_DEBUG
including CLKOUT mux. So we can use the exynos4's clkout init
function for Exynos3250 without the need to add new function.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
This patch fixes the bug of CLK_SCLK_HDMI_SPDIF_DISP clock because this clock
should be included in CMU_TOP domain. So, this patch moves the CLK_SCLK_HDMI_
SPDIF_DISP clock from CMU_MIF to CMU_TOP domain.
Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which
generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which
generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_ISP domain which
generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which
generates the clocks for HEVC(High Efficiency Video Codec) decoder IP.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_MFC domain which
generates the clocks for MFC(Multi-Format Codec) IP.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain
which generates the clocks for Cortex-A53 Quad-core processsor.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for register accesses.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the the mux/divider/gate clocks for CMU_DISP domain
which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER).
Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP
domain. This patch adds the clocks of CMU_TOP related to HDMI.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which
includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in
the CMU_TOP domain. Hence this patch adds G2D related clocks to the
CMU_TOP domain.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use oscclk source clock directly.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds support for the CMU (Clock Management Units) of Exynos5433
which is an Octa-core 64bit SoC. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h]
[ added U suffix to first arguments of PLL_35XX_RATE()]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
and addition of clock definitions for DVFS on Exynos4.
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Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung into clk-next
Exynos 3250, 4415 drivers cleanup by using common code
and addition of clock definitions for DVFS on Exynos4.
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:
ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)
Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling)
feature of the exynos memory bus.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.
Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch uses the samsung_cmu_register_one() to simplify code
for Exynos4415.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch uses the samsung_cmu_register_one() to simplify code
for Exynos3250.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch changes the return value of samsung_cmu_register_one()
from 'void' to 'samsung_clk_provider structure' pointer type because
samsung_clk_provider may be used in each clock driver.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add clock support for the MSCL block for Exynos7.
Signed-off-by: Tony K Nadackal <tony.kn@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
much later than usual due to several last minute bugs that had to be
addressed. As usual the majority of changes are new drivers and
modifications to existing drivers. The core recieved many fixes along
with the groundwork for several large changes coming in the future which
will better parition clock providers from clock consumers.
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Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework updates from Mike Turquette:
"This is much later than usual due to several last minute bugs that had
to be addressed. As usual the majority of changes are new drivers and
modifications to existing drivers. The core recieved many fixes along
with the groundwork for several large changes coming in the future
which will better parition clock providers from clock consumers"
* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
ARM: OMAP3: clock: fix boot breakage in legacy mode
ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
clk: Really fix deadlock with mmap_sem
clk: mmp: fix sparse non static symbol warning
clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
clk: change clk_debugfs_add_file to take a struct clk_hw
clk: Don't expose __clk_get_accuracy
clk: Don't try to use a struct clk* after it could have been freed
clk: Remove unused function __clk_get_prepare_count
clk: samsung: Fix double add of syscore ops after driver rebind
clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
clk: samsung: remove unnecessary inclusion of header files from clk.h
clk: samsung: remove unnecessary CONFIG_OF from clk.c
clk: samsung: Spelling s/bwtween/between/
clk: rockchip: Add support for the mmc clock phases using the framework
clk: rockchip: add bindings for the mmc clocks
clk: rockchip: rk3288 export i2s0_clkout for use in DT
clk: rockchip: use clock ID for DMC (memory controller) on rk3288
...
Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the "amba" clock was disabled and there
were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because
samsung_pinmux_setup() tried to access memory from audss block which was
gated.
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Here's the set of driver core patches for 3.19-rc1.
They are dominated by the removal of the .owner field in platform
drivers. They touch a lot of files, but they are "simple" changes, just
removing a line in a structure.
Other than that, a few minor driver core and debugfs changes. There are
some ath9k patches coming in through this tree that have been acked by
the wireless maintainers as they relied on the debugfs changes.
Everything has been in linux-next for a while.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core update from Greg KH:
"Here's the set of driver core patches for 3.19-rc1.
They are dominated by the removal of the .owner field in platform
drivers. They touch a lot of files, but they are "simple" changes,
just removing a line in a structure.
Other than that, a few minor driver core and debugfs changes. There
are some ath9k patches coming in through this tree that have been
acked by the wireless maintainers as they relied on the debugfs
changes.
Everything has been in linux-next for a while"
* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
fs: debugfs: add forward declaration for struct device type
firmware class: Deletion of an unnecessary check before the function call "vunmap"
firmware loader: fix hung task warning dump
devcoredump: provide a one-way disable function
device: Add dev_<level>_once variants
ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
ath: use seq_file api for ath9k debugfs files
debugfs: add helper function to create device related seq_file
drivers/base: cacheinfo: remove noisy error boot message
Revert "core: platform: add warning if driver has no owner"
drivers: base: support cpu cache information interface to userspace via sysfs
drivers: base: add cpu_device_create to support per-cpu devices
topology: replace custom attribute macros with standard DEVICE_ATTR*
cpumask: factor out show_cpumap into separate helper function
driver core: Fix unbalanced device reference in drivers_probe
driver core: fix race with userland in device_add()
sysfs/kernfs: make read requests on pre-alloc files use the buffer.
sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
fs: sysfs: return EGBIG on write if offset is larger than file size
...
sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
The patch models this dependency using parent/child hirerarchy.
The patch fixes issue with system hangs during mixer device access, mixer uses
sclk_hdmiphy descendant clock.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Fix following build errors when PM_SLEEP is disabled (e.g. by disabling
SUSPEND and HIBERNATION):
drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’:
drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function)
drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’:
drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function)
make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Let's remove unnecessary include of header files from clk.h and add
required one in clk.c
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
[s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>']
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Let's register restart handler for Exynos5440 from it's clock driver
for restart functionality. So that we can cleanup restart hooks from
machine specific file.
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add clock support for the ADC interface in Exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to
"struct exynos_cmu_info" to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
and rockchip as well as s3c24xx restart handlers.
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Merge tag 'v3.18-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Allow parent rate changes for i2s on rk3288
and rockchip as well as s3c24xx restart handlers.
S3C2412, S3C2443 and their derivatives contain a special software-reset
register in their system-controller.
Therefore register a restart handler for those.
Tested on a s3c2416-based board, s3c2412 compile-tested.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
There is no need to init .owner field.
Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"
This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
This patch adds support for exporting mout_hdmi and mout_mixer to device
tree. Access to those clocks is required to correctly setup HDMI module
on Exynos 4210 and 4x12 SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: Mike Turquette <mturquette@linaro.org>
CC: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.
The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
This is the bulk of new SoC enablement and other platform changes for 3.17:
* Samsung S5PV210 has been converted to DT and multiplatform
* Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
* Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood.
* Hwmod data for TI AM43xx and DRA7 platforms.
* More additions of Renesas shmobile platform support
* Removal of plat-samsung contents that can be removed with S5PV210 being
multiplatform/DT-enabled and the other two old platforms being removed.
New platforms (most with only basic support right now):
* Hisilicon X5HD2 settop box chipset is introduced
* Mediatek MT6589 (mobile chipset) is introduced
* Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This is the bulk of new SoC enablement and other platform changes for
3.17:
- Samsung S5PV210 has been converted to DT and multiplatform
- Clock drivers and bindings for some of the lower-end i.MX 1/2
platforms
- Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood
- Hwmod data for TI AM43xx and DRA7 platforms
- More additions of Renesas shmobile platform support
- Removal of plat-samsung contents that can be removed with S5PV210
being multiplatform/DT-enabled and the other two old platforms
being removed
New platforms (most with only basic support right now):
- Hisilicon X5HD2 settop box chipset is introduced
- Mediatek MT6589 (mobile chipset) is introduced
- Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code"
* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
ARM: hisi: remove smp from machine descriptor
power: reset: move hisilicon reboot code
ARM: dts: Add hix5hd2-dkb dts file.
ARM: debug: Rename Hi3716 to HIX5HD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: add ARCH_HISI
MAINTAINERS: add entry for Broadcom ARM STB architecture
ARM: brcmstb: select GISB arbiter and interrupt drivers
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
ARM: configs: enable SMP in bcm_defconfig
ARM: add SMP support for Broadcom mobile SoCs
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
...
drivers and fixes/enhancements to existing clock drivers. There are also
some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
* improvements to printks on errors
* flattening the previously hierarchal structure of per-clock entries
in debugfs
* allow per-clock debugfs entries that are specific to a particular
clock driver
* configure initial clock parent and/or initial clock rate from Device
Tree
* several feature enhancements to the composite clock type
* misc fixes
New clock drivers added include:
* TI Palmas PMIC
* Allwinner A23 SoC
* Qualcomm APQ8084 and IPQ8064 SoCs
* Rockchip rk3188, rk3066 and rk3288 SoCs
* STMicroelectronics STiH407 SoC
* Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK down"
power saving feature for their Exynos4 & Exynos5 SoCs.
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Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are
also some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
- improvements to printks on errors
- flattening the previously hierarchal structure of per-clock entries
in debugfs
- allow per-clock debugfs entries that are specific to a particular
clock driver
- configure initial clock parent and/or initial clock rate from
Device Tree
- several feature enhancements to the composite clock type
- misc fixes
New clock drivers added include:
- TI Palmas PMIC
- Allwinner A23 SoC
- Qualcomm APQ8084 and IPQ8064 SoCs
- Rockchip rk3188, rk3066 and rk3288 SoCs
- STMicroelectronics STiH407 SoC
- Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK
down" power saving feature for their Exynos4 & Exynos5 SoCs"
* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: Add missing of_clk_set_defaults export
clk: checking wrong variable in __set_clk_parents()
clk: Propagate any error return from debug_init()
clk: clps711x: Add DT bindings documentation
clk: Add CLPS711X clk driver
clk: st: Use round to closest divider flag
clk: st: Update frequency tables for fs660c32 and fs432c65
clk: st: STiH407: Support for clockgenA9
clk: st: STiH407: Support for clockgenD0/D2/D3
clk: st: STiH407: Support for clockgenC0
clk: st: Add quadfs reset handling
clk: st: Add polarity bit indication
clk: st: STiH407: Support for clockgenA0
clk: st: STiH407: Support for A9 MUX Clocks
clk: st: STiH407: Support for Flexgen Clocks
clk: st: Adds Flexgen clock binding
clk: st: Remove uncessary (void *) cast
clk: st: use static const for clkgen_pll_data tables
clk: st: use static const for stm_fs tables
clk: st: Update ST clock binding documentation
...
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: Arjun K.V <arjun.kv@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
while at it, add these clks to save/restore list also.
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor.
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
- Trats2: 6.5% (153 mA -> 143 mA)
- Trats: 33.0% (180 mA -> 120 mA)
- Gear1: 27.0% (180 mA -> 130 mA)
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.
Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Daniel Drake <drake@endlessm.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds missing definitions of clocks from CPU and DMC clock
domains, which are necessary to properly represent CLKOUT clock hierarchy
added in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Since there is no more support for board files, this patch removes
legacy non-DT support from the clock driver as well, including
unnecessary clkdev aliases.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a driver for clock controller being a part of Audio
Subsystem present on S5PV210 and compatible SoCs. It is used to provide
clocks for other IP blocks of this subsystem.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 and compatible SoCs. The driver is just added, without enabling it yet.
Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[t.figa: Added support for other SoC variants and clock output. Fixed
remaining minor issues.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Samsung, ST & TI. Most of them are of the "this hardware won't work
without this fix" variety, including patches that fix platforms that did
not boot under certain configurations. Other fixes are the result of
changes to the clock core introduced in 3.15 that had subtle impacts on
the clock drivers.
There are no fixes to the clock framework core in this pull request.
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Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock driver fixes from Mike Turquette:
"This batch of fixes is for a handful of clock drivers from Allwinner,
Samsung, ST & TI. Most of them are of the "this hardware won't work
without this fix" variety, including patches that fix platforms that
did not boot under certain configurations. Other fixes are the result
of changes to the clock core introduced in 3.15 that had subtle
impacts on the clock drivers.
There are no fixes to the clock framework core in this pull request"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: spear3xx: Set proper clock parent of uart1/2
clk: spear3xx: Use proper control register offset
clk: qcom: HDMI source sel is 3 not 2
clk: sunxi: fix devm_ioremap_resource error detection code
clk: s2mps11: Fix double free corruption during driver unbind
clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
clk: exynos5420: Remove aclk66_peric from the clock tree description
clk/exynos5250: fix bit number for tv sysmmu clock
clk: s3c64xx: Hookup SPI clocks correctly
clk: samsung: exynos4: Remove SRC_MASK_ISP gates
clk: samsung: add more aliases for s3c24xx
clk: samsung: fix several typos to fix boot on s3c2410
clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
clk: ti: dra7: return error code in failure case
clk: ti: apll: not allocating enough data
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
