clk_unregister() is currently not implemented and it is required when
a clock provider module needs to be unloaded.
Normally the clock supplier module is prevented to be unloaded by
taking reference on the module in clk_get().
For cases when the clock supplier module deinitializes despite the
consumers of its clocks holding a reference on the module, e.g. when
the driver is unbound through "unbind" sysfs attribute, there are
empty clock ops added. These ops are assigned temporarily to struct
clk and used until all consumers release the clock, to avoid invoking
callbacks from the module which just got removed.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This patch adds common __clk_get(), __clk_put() clkdev helpers that
replace their platform specific counterparts when the common clock
API is used.
The owner module pointer field is added to struct clk so a reference
to the clock supplier module can be taken by the clock consumers.
The owner module is assigned while the clock is being registered,
in functions _clk_register() and __clk_register().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is currently a race condition in the device tree part of clk_get()
function, since the pointer returned from of_clk_get_by_name() may become
invalid before __clk_get() call. E.g. due to the clock provider driver
remove() callback being called in between of_clk_get_by_name() and
__clk_get().
Fix this by doing both the look up and __clk_get() operations with the
clock providers list mutex held. This ensures that the clock pointer
returned from __of_clk_get_from_provider() call and passed to __clk_get()
is valid, as long as the clock supplier module first removes its clock
provider instance and then does clk_unregister() on the corresponding
clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add helper functions for the of_clk_providers list locking and
an unlocked variant of of_clk_get_from_provider().
These functions are intended to be used in the clkdev to avoid
race condition in the device tree based clock look up in clk_get().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
The clock core code is going to be modified so clk_get() takes
reference on the clock provider module. Until the potential circular
reference issue is properly addressed, we pass NULL as the first
argument to clk_register(), in order to disallow sub-devices taking
a reference on the ISP module back trough clk_get(). This should
prevent locking the modules in memory.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.
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Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next-sunxi-rebase
Allwinner sunXi SoCs clock changes
Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.
Conflicts:
drivers/clk/sunxi/clk-sunxi.c
In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The required properties are not named "div" and "mult",
but rather "clock-div" and "clock-mult".
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[Maybe the third time will be the charm. -Alex]
If CONFIG_COMMON_CLK_DEBUG is defined, clk_debug_create_one() is
called to populate a debugfs directory with a few entries that are
common for all clock types.
If an error happens after creating the first one debugfs_remove() is
called on the clock's directory. The problem with this is that no
cleanup is done on the debugfs files already created in that
directory, so the directory never actually gets removed. This
problem is silently ignored.
Fix this by calling debugfs_remove_recursive() instead. Reset the
clk->dentry field to null afterward, to ensure it can't be mistaken
as a valid pointer.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: Thierry Reding <treding@nvidia.com>
There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.
This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: Thierry Reding <treding@nvidia.com>
These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock. We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
