mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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clk: tegra: move PMC, fixed clocks to common files
Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
This commit is contained in:
Peter De Schrijver
parent
76ebc134d4
commit
de4f30fd84
@ -8,6 +8,8 @@ obj-y += clk-pll-out.o
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obj-y += clk-super.o
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obj-y += clk-tegra-audio.o
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obj-y += clk-tegra-periph.o
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obj-y += clk-tegra-pmc.o
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obj-y += clk-tegra-fixed.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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111
drivers/clk/tegra/clk-tegra-fixed.c
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111
drivers/clk/tegra/clk-tegra-fixed.c
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@ -0,0 +1,111 @@
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/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define OSC_CTRL 0x50
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
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int __init tegra_osc_clk_init(void __iomem *clk_base,
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struct tegra_clk *tegra_clks,
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unsigned long *input_freqs, int num,
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unsigned long *osc_freq,
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unsigned long *pll_ref_freq)
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{
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struct clk *clk;
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struct clk **dt_clk;
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u32 val, pll_ref_div;
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unsigned osc_idx;
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val = readl_relaxed(clk_base + OSC_CTRL);
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osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
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if (osc_idx < num)
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*osc_freq = input_freqs[osc_idx];
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else
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*osc_freq = 0;
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if (!*osc_freq) {
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WARN_ON(1);
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return -EINVAL;
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}
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);
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if (!dt_clk)
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return 0;
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clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
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*osc_freq);
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*dt_clk = clk;
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/* pll_ref */
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val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
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pll_ref_div = 1 << val;
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);
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if (!dt_clk)
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return 0;
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clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
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0, 1, pll_ref_div);
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*dt_clk = clk;
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if (pll_ref_freq)
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*pll_ref_freq = *osc_freq / pll_ref_div;
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return 0;
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}
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void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
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{
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struct clk *clk;
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struct clk **dt_clk;
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/* clk_32k */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
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CLK_IS_ROOT, 32768);
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*dt_clk = clk;
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}
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/* clk_m_div2 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
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CLK_SET_RATE_PARENT, 1, 2);
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*dt_clk = clk;
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}
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/* clk_m_div4 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
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CLK_SET_RATE_PARENT, 1, 4);
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*dt_clk = clk;
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}
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}
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132
drivers/clk/tegra/clk-tegra-pmc.c
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132
drivers/clk/tegra/clk-tegra-pmc.c
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@ -0,0 +1,132 @@
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/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define PMC_CLK_OUT_CNTRL 0x1a8
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#define PMC_DPD_PADS_ORIDE 0x1c
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#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
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#define PMC_CTRL 0
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#define PMC_CTRL_BLINK_ENB 7
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#define PMC_BLINK_TIMER 0x40
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struct pmc_clk_init_data {
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char *mux_name;
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char *gate_name;
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const char **parents;
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int num_parents;
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int mux_id;
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int gate_id;
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char *dev_name;
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u8 mux_shift;
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u8 gate_shift;
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};
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#define PMC_CLK(_num, _mux_shift, _gate_shift)\
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{\
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.mux_name = "clk_out_" #_num "_mux",\
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.gate_name = "clk_out_" #_num,\
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.parents = clk_out ##_num ##_parents,\
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.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
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.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
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.gate_id = tegra_clk_clk_out_ ##_num,\
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.dev_name = "extern" #_num,\
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.mux_shift = _mux_shift,\
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.gate_shift = _gate_shift,\
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}
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static DEFINE_SPINLOCK(clk_out_lock);
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static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern1",
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};
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static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern2",
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};
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static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern3",
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};
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static struct pmc_clk_init_data pmc_clks[] = {
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PMC_CLK(1, 6, 2),
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PMC_CLK(2, 14, 10),
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PMC_CLK(3, 22, 18),
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};
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void __init tegra_pmc_clk_init(void __iomem *pmc_base,
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struct tegra_clk *tegra_clks)
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{
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struct clk *clk;
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struct clk **dt_clk;
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int i;
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for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
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struct pmc_clk_init_data *data;
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data = pmc_clks + i;
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dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_mux(NULL, data->mux_name, data->parents,
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data->num_parents, CLK_SET_RATE_NO_REPARENT,
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pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
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3, 0, &clk_out_lock);
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*dt_clk = clk;
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dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
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0, pmc_base + PMC_CLK_OUT_CNTRL,
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data->gate_shift, 0, &clk_out_lock);
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*dt_clk = clk;
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clk_register_clkdev(clk, data->dev_name, data->gate_name);
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}
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/* blink */
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writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
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clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
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pmc_base + PMC_DPD_PADS_ORIDE,
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PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
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dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
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if (!dt_clk)
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return;
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clk = clk_register_gate(NULL, "blink", "blink_override", 0,
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pmc_base + PMC_CTRL,
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PMC_CTRL_BLINK_ENB, 0, NULL);
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clk_register_clkdev(clk, "blink", NULL);
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*dt_clk = clk;
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}
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@ -107,13 +107,6 @@
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#define PLLC_OUT 0x84
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#define PLLM_OUT 0x94
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#define PMC_CLK_OUT_CNTRL 0x1a8
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#define PMC_DPD_PADS_ORIDE 0x1c
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#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
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#define PMC_CTRL 0
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#define PMC_CTRL_BLINK_ENB 7
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#define PMC_BLINK_TIMER 0x40
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#define OSC_CTRL 0x50
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
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@ -177,7 +170,6 @@ static DEFINE_SPINLOCK(pll_d_lock);
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static DEFINE_SPINLOCK(pll_d2_lock);
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static DEFINE_SPINLOCK(pll_u_lock);
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static DEFINE_SPINLOCK(pll_re_lock);
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static DEFINE_SPINLOCK(clk_out_lock);
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static DEFINE_SPINLOCK(sysrate_lock);
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static struct div_nmp pllxc_nmp = {
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@ -1199,71 +1191,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
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clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
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}
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static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern1",
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};
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static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern2",
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};
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static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern3",
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};
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static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
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{
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struct clk *clk;
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/* clk_out_1 */
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clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
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ARRAY_SIZE(clk_out1_parents),
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CLK_SET_RATE_NO_REPARENT,
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pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk;
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clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_1] = clk;
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/* clk_out_2 */
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clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
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ARRAY_SIZE(clk_out2_parents),
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CLK_SET_RATE_NO_REPARENT,
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pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk;
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clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_2] = clk;
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/* clk_out_3 */
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clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
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ARRAY_SIZE(clk_out3_parents),
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CLK_SET_RATE_NO_REPARENT,
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pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk;
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clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
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pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
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&clk_out_lock);
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clks[TEGRA114_CLK_CLK_OUT_3] = clk;
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/* blink */
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/* clear the blink timer register to directly output clk_32k */
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writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
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clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
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pmc_base + PMC_DPD_PADS_ORIDE,
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PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
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clk = clk_register_gate(NULL, "blink", "blink_override", 0,
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pmc_base + PMC_CTRL,
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PMC_CTRL_BLINK_ENB, 0, NULL);
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clks[TEGRA114_CLK_BLINK] = clk;
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}
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static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
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"pll_p", "pll_p_out2", "unused",
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"clk_32k", "pll_m_out1" };
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@ -1612,7 +1539,7 @@ static void __init tegra114_clock_init(struct device_node *np)
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tegra114_pll_init(clk_base, pmc_base);
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tegra114_periph_clk_init(clk_base, pmc_base);
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tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
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tegra114_pmc_clk_init(pmc_base);
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tegra_pmc_clk_init(pmc_base, tegra114_clks);
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tegra114_super_clk_init(clk_base);
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tegra_add_of_provider(np);
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@ -604,6 +604,13 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
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struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *pll_params);
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void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
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void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
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int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
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unsigned long *input_freqs, int num,
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unsigned long *osc_freq,
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unsigned long *pll_ref_freq);
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void tegra114_clock_tune_cpu_trimmers_high(void);
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void tegra114_clock_tune_cpu_trimmers_low(void);
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void tegra114_clock_tune_cpu_trimmers_init(void);
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