If the .debug_init op is provided, it will be called by
clk_debug_create_one(). If debug_init() returns an error code,
clk_debug_create_one() will return -ENOMEM, regardless of the
value returned from debug_init(). Tweak the code to return
the actual value returned by debug_init() instead.
Signed-off-by: Chris Brand <chris.brand@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This adds the clock driver for Cirrus Logic CLPS711X series SoCs
using common clock infrastructure.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch uses CLK_DIVIDER_ROUND_CLOSEST flag to specify
the divider has to round to closest div.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch extend the range of possible frequencies of the fs432c65
and fs660c32 Quad frequency synthesizers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch added support for ClockGenD0/D2/D3
It includes one 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds the support of quadfs reset handling.
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch supports the A9-mux clocks used by ClockGenA9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.
The idea is to have an instance of "struct flexgen" per output clock.
It represents the clock cross bar (by a mux element), and the pre and final dividers
(using dividers and gates elements).
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
converts clkgen_pll_data tables into static const
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
converts stm_fs tables into static const
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch corrects mistyped author's name in four header files. While
at it, a copy/paste error in author's e-mail in one of the headers is
also fixed.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: Arjun K.V <arjun.kv@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
while at it, add these clks to save/restore list also.
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor.
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
- Trats2: 6.5% (153 mA -> 143 mA)
- Trats: 33.0% (180 mA -> 120 mA)
- Gear1: 27.0% (180 mA -> 130 mA)
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.
Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Daniel Drake <drake@endlessm.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch extends nodes of PMU system controller on Exynos4210, 4x12,
5250 and 5420 SoCs with newly defined properties used by Exynos CLKOUT
driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJTyYx4AAoJEBx+YmzsjxAgj9QP/2zRnM312oQ0MPPys+QG8mLg
Ecsi+RVuCnfk3+JGqvvh0FRkyNinK4KHitPc2YAvK07vOjwhalYNfFRtuK4MRgmW
z217GHzr67GJuu5nn6xlP1c6NYSZEtImvbksnthE4SPXrxA56fp4FME9/I4/vOR+
/+5KNWHCfngfZTBVFvjeXAh/pNXEdYBpPqe/CQCmhjDW8rxJJAVoFCAXA+Xx2ln/
StJXnSQdiJtoDLF19iaqp+W1i2xhaLF3oLUcEoqL3/ZGTTrm2ylT8dFyCb2RpIsn
6CEzVKjky6Yr851AaU+d2p/IQEUT1j35zPiLDhyZCTsEEVW91h89ykB2GjlEwH+n
cPicqfP+5/y0rnGU7JDjf4eqv/l+VX2M7/BKra2H4xLUrHXqZOSFnkidF6cdE77C
nLHfNXR4eyIfw5r7ccwd2ZMTofzNpEIAixt6/UjfpCun0u1uFI54/vfEoXvcyemm
IggOmah8BMogMG8ZhDHgQo5ln8JFjULkackAcwQL+a1qLZW601NOsa9Ke0xuCkEE
lXw+JytWUwz+D+hxB5XAvYMLNRXZ4WuIY/VO4SfNR6fdc+9bs0QN942QA7T+46g2
SvUFml/9sbGKFOBRWx+sEebxoLz0jnt7FqxRU4z0ZK0W6qLiNs4TeIOy5JpxPCAE
lEAwP7hv5da8InxsSlxR
=85He
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi
Allwinner clocks additions for 3.17
This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
This patch adds missing definitions of clocks from CPU and DMC clock
domains, which are necessary to properly represent CLKOUT clock hierarchy
added in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
These patches add support for a handful of Qualcomm's SoC clock
controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
There's also a small collection of bug fixes that aren't critical
-rc worthy regressions because the consumer drivers aren't present
or using the buggy clocks and one optimization for HDMI.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABCAAGBQJTyb5mAAoJENidgRMleOc9mCAP/3JAiwaf0vsdhxf5/hQRakTq
DzGnjtMV3fHvEc5vBO5mdv8uiOv6P6dkWdBh2cRk52sFgdqz+qcr4IfQUw7yVUDN
Zyr9BqrrEEllQLTRbzf/8cEIWyXripp7kV7yVjP2Ng37NPktliYb26sqp2HODeEa
38+yi/gXbUQ5Gzh0EIeUmt1ORpJfa9qGlxRQGuDT+wL35Fb6Q/Lr+emfacmVkJuO
FYOXRHVK1i3WnjigCATsYmoD5jFkpGBqJgUFfzyy5oz94WrL6QRrSbQS3ASsWx2i
c2tSXvrOSX9Xf9/UOjf6ZZ+5qvdjxWOHkkilerbJDEUnV4W9G8dmag/7czUINVmU
/21KUoObj+wLdWl4SFMdUmksGkHLm7j6Tnllfkcke3FQrELovfb4ARAsxiU2zvXy
646qfk7f+0SWPf3/3fKl9JEQnqBaOimDjX6ibbHjY16r4xiCVMzACVeI3CQtlFyZ
knMQVjZDcgj1w80SSuG60e3Ahd5rknH8eB2h+nrUtbbjz2S1u733Dht4vBgDkSHZ
yntZ/u/7HhNehqjlBWBQyLuTPRIBTENQW2W95QR9W62FaQgzZXd7/n74gcoS3CsG
pqI1Glb166GbmiEtbXEKrOIwMenOiR7RY1/BsKO0kAqJitrShy8mvqTEzFyDPZo5
HdqttkTPpDGcF53PtltY
=azpb
-----END PGP SIGNATURE-----
Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm
qcom clock changes for 3.17
These patches add support for a handful of Qualcomm's SoC clock
controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
There's also a small collection of bug fixes that aren't critical
-rc worthy regressions because the consumer drivers aren't present
or using the buggy clocks and one optimization for HDMI.
This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.
Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.
Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.
Fixes: 49fc825f0c "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.
Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In the case of HDMI clocks, we want to bypass the RCG's ability
to divide the output clock and pass through the parent HDMI PLL
rate. Add a simple set of clk_ops to configure the RCG to do
this. This removes the need to keep adding more frequency entries
to the tv_src clock whenever we want to support a new rate.
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.
This is currently missing clocks for USB HSIC and networking devices.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
sun6i-apb0-gates uses the "clock-indices" DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.
This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
consistent with the sunxi platform. Also add the missing call to
clk_register_clkdev, so system clock lookups will work.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All known Rockchip SoCs have a reset controller in their CRUs, so it's
helpful to have the reset controller framework selected by default,
only be deselected by the user in special cases.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add the clock tree definition for the new rk3288 SoC.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This adds the dt-binding documentation for the clock and reset unit found on
Rockchip rk3288 SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This adds a clock driver that handles the specific muxes, dividers and gates
of rk3188 and rk3066 SoCs.
The structure of the clock list resembles the arrangement of their
counterparts in the clock architecture diagrams found in the SoC
documentation.
Clocks exported to the clock provider are currently limited to well known
or measured ones. So additional clock exports may be necessary in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
