I missed the fact that these constants was not yet available, so hard
code their values in the dts to make the branch compile on its own.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
APQ8096 has its VDD APC (Power for quad Kryo applications
microprocessors) powered by PM8996 PMIC S9, S10, S11 tri-phase
regulators (gang). The bootloader may have configured these
regulators with non sustainable default values, leading to sporadic
hangs under CPU stress tests (cpufreq-bench). Ideally we should enable
voltage scaling along with frequency scaling, but for now just set the
regulator gang value to a sane voltage, capable of supporting highest
frequencies (turbo).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Link: https://lore.kernel.org/r/1578401755-26211-1-git-send-email-loic.poulain@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
vdd_apc is the regulator that supplies the main CPU cluster.
At sudden CPU load changes, we have noticed invalid page faults on
addresses with all bits shifted, as well as on addresses with individual
bits flipped.
By putting the vdd_apc regulator in high power mode, the voltage drops
during sudden load changes will be less severe, and we have not been able
to reproduce the invalid page faults with the regulator in this mode.
Fixes: 8faea8edbb ("arm64: dts: qcom: qcs404-evb: add spmi regulators")
Cc: stable@vger.kernel.org
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20191014120920.12691-1-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The msm_serial driver has a predefined set of uart ports defined, which
is allocated either by reading aliases or if no match is found a simple
counter, starting at index 0. But there's no logic in place to prevent
these two allocation mechanism from colliding. As a result either none
or all of the active msm_serial instances must be listed as aliases.
Define blsp1_uart3 as "serial1" to mitigate this problem.
Fixes: 4cffb9f2c7 ("arm64: dts: qcom: msm8998-mtp: Enable bluetooth")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191119011823.379100-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fix the following error/warn seen with make dtbs_check
arm,smmu-venus@d40000: $nodename:0: 'arm,smmu-venus@d40000' does not match '^iommu@[0-9a-f]*'
arm,smmu-venus@d40000: clock-names:0: 'bus' was expected
arm,smmu-venus@d40000: clock-names:1: 'iface' was expected
by rename nodename to "iommu".
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Link: https://lore.kernel.org/r/20200106102305.27059-1-stanimir.varbanov@linaro.org
[bjorn: Added padding of address to 8 digits]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
UFS phy register space size is 0x1c0. so update it
Reported-by: Can Guo <cang@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200106070826.147064-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Support dynamic voltage and frequency scaling on qcs404.
CPUFreq will soon be superseded by Core Power Reduction (CPR, a form
of Adaptive Voltage Scaling found on some Qualcomm SoCs like the
qcs404).
Due to the CPR upstreaming already being in progress - and some
commits already merged - the following commit will need to be
reverted to enable CPUFreq support
Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-5-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The high frequency pll functionality is required to enable CPU
frequency scaling operation.
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.
The driver still supports the previous bindings; however with this
update it we allow the msm8916 to access the parent clock names
required by the driver operation using the device tree node.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-2-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the DT node for the rpmhpd power controller on SC7180 SoCs.
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191220064823.6115-3-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the SPMI regulator node in the PM8004 LSID5 (as there is where
it resides basically 99% of the times) and set the nodes to be
disabled by default, as not all boards have both or one of the
lsids specified in this generic pm8004 DT.
While at it, also add nice phandles to the lsids specified in this
DT to allow configuration in specific board dts in a more human
readable fashion.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031111645.34777-3-kholk11@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The redistributable firmware should work on any engineering device, so
lets push this to qcom/sdm845, rather than qcom/db845c. Also specify the
path for the modem firmware.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191113203951.3704428-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Introduce a base dts for the Inforce 6640 Single Board Computer. This
initial commit boots to console on the uart and provides UFS and SD card
storage support.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Update the regulator names in db820c.dtsi to use the names from the
schematics, instead of the made up genric names.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it
easier to ensure ordering when adding new nodes.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Rather than scattering pinctrl definitions in various files, merge the
nodes into db820c.dtsi to make it easier to navigate.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Sort all nodes in db820c.dtsi based on address, then name.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Prior refactoring have left a few root nodes scattered throughout
db820c.dtsi, group these at the top of the file.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
As the definition of available PMICs and the names of their outputs are
board specifc move this to db820c.dtsi
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Supplies for the various components in the SoC depends on board layout,
so move the supply definitions to db820c.dtsi instead of carrying them
in the platform dtsi.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Instead of mimicing the structure of the platform, reference nodes by
their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where
necessary.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The USB id pins and wlan regulator are not platform devices, so move
them out of /soc
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The WiFi firmware used on db845c implements the 8bit host-capability
message, so enable the quirk for this.
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191113232245.4039932-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is just like commit ac00546a67 ("arm64: dts: qcom: sc7180:
Rename gic-its node to msi-controller") but for sdm845. This fixes
all arm64/qcom device trees that I could find.
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Update existing and add missing regions to the reserved memory map, as
described in version 7.1
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191218132217.28141-5-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Commit f4a73f5e26 ("pinctrl: qcom: sc7180: Add new qup functions")
has landed which means that we absolutely need to use the proper names
for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it.
For reference:
- If you get only one of this commit and the pinctrl commit then none
of I2C/UART 2, 4, 7, and 9 will work.
- If you get neither of these commits then I2C 2, 4, 7, and 9 will
work but not UART.
...but despite the above it should be fine for this commit to land in
the Qualcomm tree because sc7180.dtsi only exists there (it hasn't
made it to mainline).
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Fixes: ba3fc64963 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191217130352.1.Id8562de45e8441cac34699047e25e7424281e9d4@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU.
This should be hooked up to the GPU CPR, but we don't have support for that
yet, so until then, just turn on the regulator and keep it on so that we
can focus on basic GPU bringup.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191217170249.5280-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The SC7180 device tree nodes should be ordered by address. Re-shuffle
some nodes which currently don't follow this convention.
Since we are already moving it add a missing leading zero to the
address in the 'reg' property of the 'interrupt-controller@b220000'
node.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212170824.v2.1.I55198466344789267ed1eb5ec555fd890c9fc6e1@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
It turns out that the wcn3990 can float the gpio lines during bootup, etc
which will result in the uart core thinking there is incoming data. This
results in the bluetooth stack getting garbage. By applying a bias to
match what wcn3990 would drive, the issue is corrected.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191021161921.31825-1-jeffrey.l.hugo@gmail.com
[bjorn: Moved board specific pinctrl states to the end]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the cr50 device to the spi controller it is attached to. This
enables /dev/tpm0 and some login things on Cheza.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20191216234204.190769-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The bindings for the QMP PHY are truly strange. I believe (?) that
they may have originated because with PCIe each lane is treated as a
different PHY and the same PHY driver is used for a whole bunch of
things (incluidng PCIe).
In any case, now that we have "make dtbs_check", we find that having
the outer node named "phy" triggers the
"schemas/phy/phy-provider.yaml" schema, yelling about:
phy@88e9000: '#phy-cells' is a required property
Let's call the outer node the "phy-wrapper" and the inner node the
"phy" to make dtbs_check happy.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 0b766e7fe5 ("arm64: dts: qcom: sc7180: Add USB related nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.6.Iec10b23bb000186b36b8bacfb6789d8233de04a7@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is just like commit e77cc85ee3 ("arm64: dts: qcom: sdm845:
remove macro from unit name"). It fixes the error in 'make
dtbs_check':
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: adc@3100: 'adc-chan@0x06' does not match any of the regexes: ...
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: a727ec1232 ("arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.4.I5f67a5ed7665f658c95447a837cbd0021e1dc689@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Running "dtbs_check" yells:
'#clock-cells' is a dependency of 'clock-output-names'
...and sure enough the bindings say we should have "#clock-cells".
Add it.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 0b766e7fe5 ("arm64: dts: qcom: sc7180: Add USB related nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.3.Ia530e4065ca81f55ac8f89a400f6a0a084ff6712@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Running `make dtbs_check` yells:
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: interrupt-controller@17a00000: gic-its@17a40000: False schema
From "arm,gic-v3.yaml" we can grok that this is explained by the
comment "msi-controller is preferred". Switch to the preferred name
so that dtbs_check stops yelling.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 90db71e480 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.2.Ibad7d3b0bea02957e89047942c61cc6c0aa61715@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
