The rv4162 vendor is microcrystal, not ST.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the more specific QuadPlus compatible to the GPC node, to trigger the
required workarounds in the power domain code.
In regard to the interrupt mapping the QuadPlus controller is fully
compatible to the Quad one, so keep that compatible in place.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove the sky2 ethernet device node from the pcie controller which was
invalid to begin with.
The original intent was to allow the bootloader to populate the MAC via
dt but this requires the PCI bus topology to be complete in dt as well
and as these boards have an expansion connector that topology is dynamic
and can't be represented here.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The board file for imx6sx-sdb overrides cpufreq operating points to use
higher voltages. This is done because the board has a shared rail for
VDD_ARM_IN and VDD_SOC_IN and when using LDO bypass the shared voltage
needs to be a value suitable for both ARM and SOC.
This only applies to LDO bypass mode, a feature not present in upstream.
When LDOs are enabled the effect is to use higher voltages than necessary
for no good reason.
Setting these higher voltages can make some boards fail to boot with ugly
semi-random crashes reminiscent of memory corruption. These failures only
happen on board rev. C, rev. B is reported to still work.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Fixes: 54183bd7f7 ("ARM: imx6sx-sdb: add revb board and make it default")
Cc: stable@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently the following errors are seen:
[ 14.015056] mc13xxx 0-0008: Failed to read IRQ status: -6
[ 27.321093] mc13xxx 0-0008: Failed to read IRQ status: -6
[ 27.411681] mc13xxx 0-0008: Failed to read IRQ status: -6
[ 27.456281] mc13xxx 0-0008: Failed to read IRQ status: -6
[ 30.527106] mc13xxx 0-0008: Failed to read IRQ status: -6
[ 36.596900] mc13xxx 0-0008: Failed to read IRQ status: -6
Also when reading the interrupts via 'cat /proc/interrupts' the
PMIC GPIO interrupt counter does not stop increasing.
The reason for the storm of interrupts is that the PUS field of
register IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT5 is currently configured as:
10 : 100k pullup
and the PMIC interrupt is being registered as IRQ_TYPE_LEVEL_HIGH type,
which is the correct type as per the MC34708 datasheet.
Use the default power on value for the IOMUX, which sets PUS field as:
00: 360k pull down
This prevents the spurious PMIC interrupts from happening.
Commit e1ffceb078 ("ARM: imx53: qsrb: fix PMIC interrupt level")
correctly described the irq type as IRQ_TYPE_LEVEL_HIGH, but
missed to update the IOMUX of the PMIC GPIO as pull down.
Fixes: e1ffceb078 ("ARM: imx53: qsrb: fix PMIC interrupt level")
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rockchip finally named the SOC as RV1108, so change it
for compatible.
The rk1108/rv1108 is completely new to the market, so there no real
devices exist in the wild, only the Rockchip internal evaluation
board. Therefore we're not breaking any existing devices when
changing compatible values.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
[added paragraph about no real devices existing]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip finally named the SOC as RV1108, so change it
for compatible.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[adapt include in rk1108-evb.dts to not introduce errors]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The R_CCU of H3/H5 currently wrongly used A64 R_CCU compatible.
Fix it by changing it to the correct H3 compatible.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This names the GPIO lines on the Banana Pi board in accordance with
the A20_Banana_Pi v1.4 Specification.
This will make these line names reflect through to user space
so that they can easily be identified and used with the new
character device ABI.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Orange Pi 2 routes the LINEOUT pins through a SGM8900 PA which
needs to be enabled. The onboard microphone is routed to MIC1, with
MBIAS providing power.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We should use hyphens and not underscores in device node names.
Replace the ones that were just added.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Kbuild now complains about leading zeroes in the address portion of
device node names.
Get rid of them all, except for the uart device node. U-boot currently
hard codes the device node path. We can remove the leading zero for
the uart once we teach U-boot to use the aliases or stdout-path
property.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.
Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.
Add device nodes and of graph nodes describing this relationship.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The NextThing Co. CHIP has an AXP209 PMIC with battery connector.
This enables the battery power supply subnode.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Sinlinx SinA33 has an AXP223 PMIC and a battery connector, thus, we
enable the battery power supply subnode in its Device Tree.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The X-Powers AXP22X PMIC exposes battery supply various data such as
the battery status (charging, discharging, full, dead), current max
limit, current current, battery capacity (in percentage), voltage max
limit, current voltage, and battery capacity (in Ah).
This adds the battery power supply subnode for AXP22X PMIC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The X-Powers AXP209 PMIC exposes battery supply various data such as
the battery status (charging, discharging, full, dead), current max
limit, current current, battery capacity (in percentage), voltage max
and min limits, current voltage, and battery capacity (in Ah).
This adds the battery power supply subnode for AXP20X PMIC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Bananapi M2 Plus has a USB OTG port that can be used in both
powered host mode and peripheral mode. When in peripheral mode,
the port does not power the board. There is no VBUS sensing on
the port.
This patch adds the regulator controlling VBUS on the OTG port,
the GPIO for the ID detect pin, and enables the USB OTG and host
controllers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Orange Pi PC, PC Plus, and Plus 2E all have a USB OTG port
that can be used in both powered host mode and peripheral mode.
When in peripheral mode, the port does not power the board.
There is no VBUS sensing on the port. All three boards have all
related pins routed the same way.
The device tree file for the Orange Pi Plus 2E is based on the
Orange Pi PC Plus, which itself is based on the Orange Pi PC.
Changes to the base Orange Pi PC device tree file affects all 3
boards.
This patch adds the regulator controlling VBUS on the OTG port,
the GPIO for the ID detect pin, and enables the USB OTG and host
controllers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the mmc0_cd_pin_reference_design pinmux setting for the default
mmc0 card detect GPIO pin.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the pinmux settings for the common regulators defined in
sunxi-common-regulators.dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The pinmux setting nodes all have an address element in their node
names, however the pinctrl node does not have #address-cells.
Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi,
dropping identifiers for functions that only have one possible setting,
and using the pingroup name if the function is identically available on
different pingroups.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
skeleton.dtsi is deprecated. Remove it from sun8i-a83t.dtsi and add
the needed device nodes directly.
Also drop an extra, non-style-conforming line in the copyright license
header.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This pull request brings back bcm2835 DT fixups from Baruch Siach that
got misplaced after a PR for 4.11 got rejected.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Now that the rockchip usb phy has a vbus-supply property use that to
control the vbus regulator on rock2.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
to me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core, mostly
small non-critical fixes here and there as well as driver updates for new
and existing hardware support. The biggest things are the TI clk driver
rework to lay the groundwork for clkctrl support in the next merge window
and the AmLogic audio/graphics clk support.
Core:
* clk_possible_parents debugfs file so we know which parents a clk
could possibly have
* Fix to make clk rate change notifiers stop on the first failure instead
of continuing
New Drivers:
* Mediatek MT6797 SoCs
* hi655x PMIC clks
* AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
* Allwinner H5 SoCs and PRCM hardware
Updates:
* Nvidia Tegra T210 cleanups and non-critical fixes
* TI OMAP cleanups in preparation for clkctrl support
* Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
* ZTE zx296718 SoC VGA clks
* Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
* Support for IDT VersaClock 5P49V5935
* Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
- mt8173: fix mmc parameters
- set timer frequency explicitly and force the driver to set it
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Merge tag 'v4.11-next-fixes' of https://github.com/mbgg/linux-mediatek into fixes
Pull "DTS fixes" from Matthias Brugger:
- mt8173: fix mmc parameters
- set timer frequency explicitly and force the driver to set it
* tag 'v4.11-next-fixes' of https://github.com/mbgg/linux-mediatek:
ARM64: dts: mediatek: configure some fixed mmc parameters
arm: dts: mt7623: add clock-frequency to the a7 timer node to mt7623.dtsi
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
changes, but also some new platforms that are worth mentioning:
* Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
Plus (Kevin)
* Orange Pi PC2 (Allwinner H5)
* Freescale LS2088A and LS1088A SoCs
* Expanded support for Nvidia Tegra186 (and Jetson TX2)
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved over
from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using arm/
and arm64/ as include prefixes. This will avoid other local hacks such as
per-file links between the two arch trees (this broke for external mirroring
of DT contents). Now they can just provide their own appropriate dt-include
hierarcy per platform.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved
over from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology
DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more
description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using
arm/ and arm64/ as include prefixes. This will avoid other local hacks
such as per-file links between the two arch trees (this broke for
external mirroring of DT contents). Now they can just provide their
own appropriate dt-include hierarcy per platform"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
ARM: dts: exynos: Use - instead of @ for DT OPP entries
arm: spear6xx: add DT description of the ADC on SPEAr600
arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
arm: spear6xx: switch spear600-evb to the new flash partition DT binding
arm: spear6xx: fix spaces in spear600-evb.dts
arm: spear6xx: use node labels in spear600-evb.dts
arm: spear6xx: add labels to various nodes in spear600.dtsi
ARM: dts: vexpress: fix few unit address format warnings
ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
ARM: dts: at91: sama5d3_xplained: fix ADC vref
ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
ARM: dts: armada-38x: label USB and SATA nodes
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
...
We need to tell the driver what the timers frequency is and that the core
has not be configured by the bootrom. Not doing so makes the unit not
boot.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Pull ARM updates from Russell King:
"Lots of little things this time:
- allow modules to be autoloaded according to the HWCAP feature bits
(used primarily for crypto modules)
- split module core and init PLT sections, since the core code and
init code could be placed far apart, and the PLT sections need to
be local to the code block.
- three patches from Chris Brandt to allow Cortex-A9 L2 cache
optimisations to be disabled where a SoC didn't wire up the out of
band signals.
- NoMMU compliance fixes, avoiding corruption of vector table which
is not being used at this point, and avoiding possible register
state corruption when switching mode.
- fixmap memory attribute compliance update.
- remove unnecessary locking from update_sections_early()
- ftrace fix for DEBUG_RODATA with !FRAME_POINTER"
* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8672/1: mm: remove tasklist locking from update_sections_early()
ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode
ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call
ARM: 8668/1: ftrace: Fix dynamic ftrace with DEBUG_RODATA and !FRAME_POINTER
ARM: 8667/3: Fix memory attribute inconsistencies when using fixmap
ARM: 8663/1: wire up HWCAP/HWCAP2 feature bits to the CPU modalias
ARM: 8666/1: mm: dump: Add domain to output
ARM: 8662/1: module: split core and init PLT sections
ARM: 8661/1: dts: r7s72100: add l2 cache
ARM: 8660/1: shmobile: r7s72100: Enable L2 cache
ARM: 8659/1: l2c: allow CA9 optimizations to be disabled
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Merge tag 'media/v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
"Media updates for v4.12-rc1:
- new driver to support mediatek jpeg in hardware codec
- rc-lirc, s5p-cec and st-cec staging drivers got promoted
- hardware histogram support for vsp1 driver
- added Virtual Media Controller driver, to make easier to test the
media controller
- added a new CEC driver (rainshadow-cec)
- removed two staging LIRC drivers for obscure hardware that are too
obsolete
- added support for Intel SR300 Depth camera
- some improvements at CEC and RC core
- lots of driver cleanups, improvements all over the tree
With this series, we're finally getting rid of the LIRC staging
driver. There's just one left (lirc_zilog), with require more care,
as part of its functionality (IR RX) is already provided by another
driver. Work in progress to convert it on the proper way"
* tag 'media/v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (304 commits)
[media] ov2640: print error if devm_*_optional*() fails
[media] atmel-isc: Fix the static checker warning
[media] ov2640: add support for MEDIA_BUS_FMT_YVYU8_2X8 and MEDIA_BUS_FMT_VYUY8_2X8
[media] ov2640: fix vflip control
[media] ov2640: fix duplicate width+height returning from ov2640_select_win()
[media] ov2640: add missing write to size change preamble
[media] ov2640: add information about DSP register 0xc7
[media] ov2640: improve banding filter register definitions/documentation
[media] ov2640: fix init sequence alignment
[media] ov2640: make GPIOLIB an optional dependency
[media] xc5000: fix spelling mistake: "calibration"
[media] vidioc-queryctrl.rst: fix menu/int menu references
[media] media-entity: only call dev_dbg_obj if mdev is not NULL
[media] pixfmt-meta-vsp1-hgo.rst: remove spurious '-'
[media] mtk-vcodec: avoid warnings because of empty macros
[media] coda: bump maximum number of internal framebuffers to 17
[media] media: mtk-vcodec: remove informative log
[media] subdev-formats.rst: remove spurious '-'
[media] dw2102: limit messages to buffer size
[media] ttusb2: limit messages to buffer size
...
Core changes:
- Add bi-directional and output-enable pin configurations to
the generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- A whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- Switch meson driver to get the GPIO ranges from the device
tree.
- Input schmitt trigger support on the Rockchip driver.
- Enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- Name the Qualcomm QDF2xxx GPIO lines.
- Support GMMR GPIO regions on the Intel Cherryview. This
fixes a serialization problem on these platforms.
- Pad retention support for the Samsung Exynos 5433.
- Handle suspend-to-ram in the AT91-pio4 driver.
- Pin configuration support in the Aspeed driver.
Cleanups:
- The final name of Rockchip RK1108 was RV1108 so rename the
driver and variables to stay consistent.
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Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.
The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.
I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.
Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.
Summary:
Core changes:
- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- switch meson driver to get the GPIO ranges from the device tree.
- input schmitt trigger support on the Rockchip driver.
- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- name the Qualcomm QDF2xxx GPIO lines.
- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.
- pad retention support for the Samsung Exynos 5433.
- handle suspend-to-ram in the AT91-pio4 driver.
- pin configuration support in the Aspeed driver.
Cleanups:
- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"
* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...
Pull networking updates from David Millar:
"Here are some highlights from the 2065 networking commits that
happened this development cycle:
1) XDP support for IXGBE (John Fastabend) and thunderx (Sunil Kowuri)
2) Add a generic XDP driver, so that anyone can test XDP even if they
lack a networking device whose driver has explicit XDP support
(me).
3) Sparc64 now has an eBPF JIT too (me)
4) Add a BPF program testing framework via BPF_PROG_TEST_RUN (Alexei
Starovoitov)
5) Make netfitler network namespace teardown less expensive (Florian
Westphal)
6) Add symmetric hashing support to nft_hash (Laura Garcia Liebana)
7) Implement NAPI and GRO in netvsc driver (Stephen Hemminger)
8) Support TC flower offload statistics in mlxsw (Arkadi Sharshevsky)
9) Multiqueue support in stmmac driver (Joao Pinto)
10) Remove TCP timewait recycling, it never really could possibly work
well in the real world and timestamp randomization really zaps any
hint of usability this feature had (Soheil Hassas Yeganeh)
11) Support level3 vs level4 ECMP route hashing in ipv4 (Nikolay
Aleksandrov)
12) Add socket busy poll support to epoll (Sridhar Samudrala)
13) Netlink extended ACK support (Johannes Berg, Pablo Neira Ayuso,
and several others)
14) IPSEC hw offload infrastructure (Steffen Klassert)"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (2065 commits)
tipc: refactor function tipc_sk_recv_stream()
tipc: refactor function tipc_sk_recvmsg()
net: thunderx: Optimize page recycling for XDP
net: thunderx: Support for XDP header adjustment
net: thunderx: Add support for XDP_TX
net: thunderx: Add support for XDP_DROP
net: thunderx: Add basic XDP support
net: thunderx: Cleanup receive buffer allocation
net: thunderx: Optimize CQE_TX handling
net: thunderx: Optimize RBDR descriptor handling
net: thunderx: Support for page recycling
ipx: call ipxitf_put() in ioctl error path
net: sched: add helpers to handle extended actions
qed*: Fix issues in the ptp filter config implementation.
qede: Fix concurrency issue in PTP Tx path processing.
stmmac: Add support for SIMATIC IOT2000 platform
net: hns: fix ethtool_get_strings overflow in hns driver
tcp: fix wraparound issue in tcp_lp
bpf, arm64: fix jit branch offset related to ldimm64
bpf, arm64: implement jiting of BPF_XADD
...
Pull crypto updates from Herbert Xu:
"Here is the crypto update for 4.12:
API:
- Add batch registration for acomp/scomp
- Change acomp testing to non-unique compressed result
- Extend algorithm name limit to 128 bytes
- Require setkey before accept(2) in algif_aead
Algorithms:
- Add support for deflate rfc1950 (zlib)
Drivers:
- Add accelerated crct10dif for powerpc
- Add crc32 in stm32
- Add sha384/sha512 in ccp
- Add 3des/gcm(aes) for v5 devices in ccp
- Add Queue Interface (QI) backend support in caam
- Add new Exynos RNG driver
- Add ThunderX ZIP driver
- Add driver for hardware random generator on MT7623 SoC"
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (101 commits)
crypto: stm32 - Fix OF module alias information
crypto: algif_aead - Require setkey before accept(2)
crypto: scomp - add support for deflate rfc1950 (zlib)
crypto: scomp - allow registration of multiple scomps
crypto: ccp - Change ISR handler method for a v5 CCP
crypto: ccp - Change ISR handler method for a v3 CCP
crypto: crypto4xx - rename ce_ring_contol to ce_ring_control
crypto: testmgr - Allow ecb(cipher_null) in FIPS mode
Revert "crypto: arm64/sha - Add constant operand modifier to ASM_EXPORT"
crypto: ccp - Disable interrupts early on unload
crypto: ccp - Use only the relevant interrupt bits
hwrng: mtk - Add driver for hardware random generator on MT7623 SoC
dt-bindings: hwrng: Add Mediatek hardware random generator bindings
crypto: crct10dif-vpmsum - Fix missing preempt_disable()
crypto: testmgr - replace compression known answer test
crypto: acomp - allow registration of multiple acomps
hwrng: n2 - Use devm_kcalloc() in n2rng_probe()
crypto: chcr - Fix error handling related to 'chcr_alloc_shash'
padata: get_next is never NULL
crypto: exynos - Add new Exynos RNG driver
...
Pull timer updates from Thomas Gleixner:
"The timer departement delivers:
- more year 2038 rework
- a massive rework of the arm achitected timer
- preparatory patches to allow NTP correction of clock event devices
to avoid early expiry
- the usual pile of fixes and enhancements all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (91 commits)
timer/sysclt: Restrict timer migration sysctl values to 0 and 1
arm64/arch_timer: Mark errata handlers as __maybe_unused
Clocksource/mips-gic: Remove redundant non devicetree init
MIPS/Malta: Probe gic-timer via devicetree
clocksource: Use GENMASK_ULL in definition of CLOCKSOURCE_MASK
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
clocksource: arm_arch_timer: add GTDT support for memory-mapped timer
acpi/arm64: Add memory-mapped timer support in GTDT driver
clocksource: arm_arch_timer: simplify ACPI support code.
acpi/arm64: Add GTDT table parse driver
clocksource: arm_arch_timer: split MMIO timer probing.
clocksource: arm_arch_timer: add structs to describe MMIO timer
clocksource: arm_arch_timer: move arch_timer_needs_of_probing into DT init call
clocksource: arm_arch_timer: refactor arch_timer_needs_probing
clocksource: arm_arch_timer: split dt-only rate handling
x86/uv/time: Set ->min_delta_ticks and ->max_delta_ticks
unicore32/time: Set ->min_delta_ticks and ->max_delta_ticks
um/time: Set ->min_delta_ticks and ->max_delta_ticks
tile/time: Set ->min_delta_ticks and ->max_delta_ticks
score/time: Set ->min_delta_ticks and ->max_delta_ticks
...
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Merge tag 'samsung-dt-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Pull "Fix DTC warnings in Exynos ARMv7 Device Tree sources." from Krzysztof Kozłowski:
* tag 'samsung-dt-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Use - instead of @ for DT OPP entries
A single fix to remove device tree warnings introduced with recently
added checks in DTC
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Merge tag 'vexpress-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Pull "ARMv7 VExpress DT fix for v4.12" from Sudeep Holla:
A single fix to remove device tree warnings introduced with recently
added checks in DTC
* tag 'vexpress-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: fix few unit address format warnings
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
A function in kernel/bpf/syscall.c which got a bug fix in 'net'
was moved to kernel/bpf/verifier.c in 'net-next'.
Signed-off-by: David S. Miller <davem@davemloft.net>
The SPEAr600 has a built-in ADC, which already has a Device Tree binding
described in
Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt. This
commit adds the description in the SPEAr600 Device Tree of this ADC
device.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
The spear6xx doesn't have a pinctrl driver, since the pinmux is globally
defined through a single register, generally configured by the
firmware/bootloader.
Therefore, the pinctrl related properties in spear600-evb.dts are not
necessary.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit moves spear600-evb.dts to use the new flash partition Device
Tree binding documented in
Documentation/devicetree/bindings/mtd/partition.txt.
As this Device Tree binding document says: "For backwards compatibility
partitions as direct subnodes of the mtd device are supported. This use
is discouraged."
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit fixes a minor coding style issue in spear600-evb.dts:
missing spaces around equal sign.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Now that we have introduced node labels in spear600.dtsi, we can use
them for spear600-evb.dts.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Having labels allows to more easily reference nodes in .dts files
including spear600.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
A bunch of clean up for Alpine device trees, nothing fancy.
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Merge tag 'alpine-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/atenart/linux into next/dt
Alpine DT changes for 4.12
A bunch of clean up for Alpine device trees, nothing fancy.
* tag 'alpine-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/atenart/linux:
ARM: dts: alpine: add valid clock-frequency values
ARM: dts: alpine: add spaces before the uart node units.
ARM: dts: alpine: remove 0x's from the uart1 node unit address
ARM: dts: alpine: fix PCIe node name
Signed-off-by: Olof Johansson <olof@lixom.net>
Use label for USB and SATA nodes on Armada 38x
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Merge tag 'mvebu-dt-4.12-3' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.12 (part 3)
Use label for USB and SATA nodes on Armada 38x
* tag 'mvebu-dt-4.12-3' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-38x: label USB and SATA nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Updates to the device tree to include upstreamed drivers:
- SPI flash controller
- Watchdog
- ADC
In addition we describe some of the clocks so that upstream kernels can
boot on hardware.
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Merge tag 'aspeed-4.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/dt
Aspeed devicetree updates for 4.12
Updates to the device tree to include upstreamed drivers:
- SPI flash controller
- Watchdog
- ADC
In addition we describe some of the clocks so that upstream kernels can
boot on hardware.
* tag 'aspeed-4.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
arm: dts: aspeed: Describe ADCs for AST2400/AST2500
ARM: dts: aspeed: romulus: Add UART1
ARM: dts: aspeed: Update watchdog compatible strings
ARM: dts: aspeed: Add a fastread property
ARM: dts: aspeed: Add SPI controller bindings to Romulus
ARM: dts: aspeed: Make G4 clocks fixed
ARM: dts: aspeed: Make G5 clocks fixed
ARM: dts: aspeed: add SPI controller bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
to configure various devices:
- Enable DCAN on am57xx-idk
- Enable CPSW ethernet0 and 1 on am335x-icev2
- Non-critical fix for droid 4 PMIC interrupt triggering
- Stop disabling SRAM and GPMC on droid 4
- Configure CPCAP PMIC related devices on droid 4 for ADC, charger
and USB PHY. The charger and USB PHY drivers are still being
discussed, but the binding for them has been acked by Rob and
Sebastian so they should be safe to merge together with the ADC
driver in Linux next that they depend on
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Merge tag 'omap-for-v4.12/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Second set of devicetree changes for omaps for v4.12 merge window
to configure various devices:
- Enable DCAN on am57xx-idk
- Enable CPSW ethernet0 and 1 on am335x-icev2
- Non-critical fix for droid 4 PMIC interrupt triggering
- Stop disabling SRAM and GPMC on droid 4
- Configure CPCAP PMIC related devices on droid 4 for ADC, charger
and USB PHY. The charger and USB PHY drivers are still being
discussed, but the binding for them has been acked by Rob and
Sebastian so they should be safe to merge together with the ADC
driver in Linux next that they depend on
* tag 'omap-for-v4.12/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-droid4: Add CPCAP PMIC OTG PHY configuration
ARM: dts: omap4-droid4: Add CPCAP PMIC battery charger configuration
ARM: dts: omap4-droid4: Add CPCAP PMIC ADC configuration
ARM: dts: omap4-droid4: Stop disabling SRAM and GPMC
ARM: dts: omap4-droid4: Fix interrupt triggering for cpcap
ARM: dts: am335x-icev2: Add CPSW ethernet0 and ethernet1
ARM: dts: am57xx-idk: Add DCAN support
Signed-off-by: Olof Johansson <olof@lixom.net>
- New board support: I2SE's i.MX28 Duckbill-2 boards, Gateworks Ventana
i.MX6 GW5903/GW5904, Zodiac Inflight Innovations RDU2 board, Engicam
i.CoreM6 Quad/Dual OpenFrame modules, Boundary Device i.MX6 Quad Plus
SOM.
- Improve compatible string for i.MX50 eSDHC, i.MX7S SRC devices and
i.MX6SX UART device.
- Add interrupts for switch and PHY devices on VF610 ZII Devel C board.
- Add LVDS, LCD backlight, touchscreen and SAI2 support for i.MX6
icore, geam, and isiot boards.
- A series from Lucas Stach to improve i.MX6Q Plus device tree and add
PRE/PRG devices.
- A series from Stefan Agner to update imx7-colibri device tree
regarding to display, PMIC/regulator support.
- Fix PCI bus DTC warnings seen with the latest compiler.
- Set default phy_type and dr_mode for i.MX25 USBOTG port.
- A couple of small improvements on i.MX25 pin function DT header.
- Add audio support for imx6q-cm-fx6 board using Wolfson wm8731 codec
which is muxed to SSI2 device.
- Other random updates, small fixes and trivial cleanups.
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Merge tag 'imx-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
i.MX device tree updates for 4.12:
- New board support: I2SE's i.MX28 Duckbill-2 boards, Gateworks Ventana
i.MX6 GW5903/GW5904, Zodiac Inflight Innovations RDU2 board, Engicam
i.CoreM6 Quad/Dual OpenFrame modules, Boundary Device i.MX6 Quad Plus
SOM.
- Improve compatible string for i.MX50 eSDHC, i.MX7S SRC devices and
i.MX6SX UART device.
- Add interrupts for switch and PHY devices on VF610 ZII Devel C board.
- Add LVDS, LCD backlight, touchscreen and SAI2 support for i.MX6
icore, geam, and isiot boards.
- A series from Lucas Stach to improve i.MX6Q Plus device tree and add
PRE/PRG devices.
- A series from Stefan Agner to update imx7-colibri device tree
regarding to display, PMIC/regulator support.
- Fix PCI bus DTC warnings seen with the latest compiler.
- Set default phy_type and dr_mode for i.MX25 USBOTG port.
- A couple of small improvements on i.MX25 pin function DT header.
- Add audio support for imx6q-cm-fx6 board using Wolfson wm8731 codec
which is muxed to SSI2 device.
- Other random updates, small fixes and trivial cleanups.
* tag 'imx-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (56 commits)
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
ARM: dts: imx7-colibri: fix PMIC voltages
ARM: dts: imx7-colibri: use OF graph to describe the display
ARM: dts: imx6qp-nitrogen6_som2: add Quad Plus variant of the SOM
ARM: dts: imx6q-icore: Add touchscreen node
ARM: dts: vf610-zii-dev-rev-b: change switch2 label
ARM: dts: imx6ul-[geam|isiot]: Add sai2 node
ARM: dts: imx6ul-isiot-common: Add touchscreen node
ARM: dts: imx6ul-isiot: Add i2c nodes
ARM: dts: imx6ul-isiot: Add imx6ul-isiot-common.dtsi
ARM: dts: imx6ul-isiot: Add backlight support for lcdif
ARM: dts: imx6ul-geam: Add backlight support for lcdif
ARM: dts: imx6: add ZII RDU2 boards
...
Signed-off-by: Olof Johansson <olof@lixom.net>
board, the phyCORE som and its PCM-947 carrier board from Phytec.
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Merge tag 'v4.12-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Support for the usb-sata controller on the rock2 and another new rk3288
board, the phyCORE som and its PCM-947 carrier board from Phytec.
* tag 'v4.12-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Add support for PCM-947 carrier board
dt-bindings: Document Phytec phyCORE-RK3288 RDK
ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM
ARM: dts: rockchip: Enable sata support on rock2 square
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Enhancements to PCIe nodes on Exynos5440.
2. Fix thermal values on some of Exynos5420 boards like Odroid XU3.
3. Add proper clock frequency properties to DSI nodes.
4. Fix watchdog reset on Exynos4412.
5. Fix watchdog infinite interrupt in soft mode on Exynos4210,
Exynos5440, S3C64xx and S5Pv210.
6. Enable watchdog on Exynos4 and S3C SoCs.
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Merge tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree ARM update for v4.12:
1. Enhancements to PCIe nodes on Exynos5440.
2. Fix thermal values on some of Exynos5420 boards like Odroid XU3.
3. Add proper clock frequency properties to DSI nodes.
4. Fix watchdog reset on Exynos4412.
5. Fix watchdog infinite interrupt in soft mode on Exynos4210,
Exynos5440, S3C64xx and S5Pv210.
6. Enable watchdog on Exynos4 and S3C SoCs.
* tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: add HDMI controller phandle to exynos4.dtsi
ARM: dts: s5pv210: Fix infinite interrupt in soft mode
ARM: dts: s3c64xx: Fix infinite interrupt in soft mode
ARM: dts: exynos: Fix infinite interrupt in soft mode on Exynos4210 and Exynos5440
ARM: dts: exynos: Enable watchdog on all Exynos4 boards
ARM: dts: s3c64xx: Enable watchdog on all S3C64xx boards
ARM: dts: exynos: Fix watchdog reset on Exynos4412
ARM: dts: exynos: Add the burst and esc clock frequency properties to DSI node
ARM: dts: exynos: Do not ignore real-world fuse values for thermal zone 0 on Exynos5420
ARM: dts: exynos: Add phy-pcie node for pcie to Exynos5440
Signed-off-by: Olof Johansson <olof@lixom.net>
Use disk-activity trigger for armada-385-linksys
Keep dts alphabetically ordered for clearfog (Armada 388)
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Merge tag 'mvebu-dt-4.12-2' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.12 (part 2)
Use disk-activity trigger for armada-385-linksys
Keep dts alphabetically ordered for clearfog (Armada 388)
* tag 'mvebu-dt-4.12-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-385-linksys: disk-activity trigger for all
ARM: dts: clearfog: keep dts alphabetically ordered
Signed-off-by: Olof Johansson <olof@lixom.net>
Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board
Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs
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Merge tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.12
Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board
Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs
* tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
ARM: dts: genmai: Enable rtc and rtc_x1 clock
ARM: dts: rskrza1: add rtc DT support
ARM: dts: rskrza1: set rtc_x1 clock value
ARM: dts: r7s72100: add rtc to device tree
ARM: dts: r7s72100: add RTC_X clock inputs to device tree
ARM: dts: r7s72100: add rtc clock to device tree
ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
ARM: dts: r8a7794: Add Z2 clock
ARM: dts: r8a7792: Correct Z clock
ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
ARM: dts: r7s72100: fix ethernet clock parent
ARM: dts: silk: Correct clock of DU1
ARM: dts: alt: Correct clock of DU1
ARM: dts: r8a7794: Correct clock of DU1
ARM: dts: r8a7794: Add DU1 clock to device tree
ARM: dts: r7s72100: add power-domains to sdhi
...
Signed-off-by: Olof Johansson <olof@lixom.net>
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
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Merge tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner H5 DT changes for 4.12
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
arm64: allwinner: h5: add support for the Orange Pi PC 2 board
arm64: allwinner: h5: add Allwinner H5 .dtsi
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
arm: sun8i: h3: split Allwinner H3 .dtsi
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
H3 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We also have some new device addition (USB, mostly) that would conflict
otherwise.
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Merge tag 'sunxi-dt-h3-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3 DT changes for 4.12
H3 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We also have some new device addition (USB, mostly) that would conflict
otherwise.
* tag 'sunxi-dt-h3-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero board
ARM: sun8i: h3: enable USB OTG on Orange Pi One
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
arm: sun8i: h3: split Allwinner H3 .dtsi
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
As usual a number of changes, among which:
- All the sun5i DTSI has been reworked based on the new documentation and
the IPs that are actually found in all those SoCs. Part of that rework
also brought the GR8 DTSI to include sun5i.dtsi
- Mali devfreq and thermal throttling support on the A33
- AC power supplies for the AXP209 and AXP22X PMIC
- CAN support for the A20
- CPUFreq-based thermal throttling for the A33
- New board: NanoPi NEO Air
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Merge tag 'sunxi-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner DT changes for 4.12
As usual a number of changes, among which:
- All the sun5i DTSI has been reworked based on the new documentation and
the IPs that are actually found in all those SoCs. Part of that rework
also brought the GR8 DTSI to include sun5i.dtsi
- Mali devfreq and thermal throttling support on the A33
- AC power supplies for the AXP209 and AXP22X PMIC
- CAN support for the A20
- CPUFreq-based thermal throttling for the A33
- New board: NanoPi NEO Air
* tag 'sunxi-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (38 commits)
ARM: sun8i: sina33: add highest OPP of CPUs
ARM: sun8i: a33: Add devfreq-based GPU cooling
ARM: sun8i: a33: add CPU thermal throttling
ARM: sun8i: a33: add thermal sensor
ARM: dts: sun7i: fix device node ordering
ARM: dts: sun4i: fix device node ordering
ARM: dts: sun7i: Add can0_pins_a pinctrl settings
ARM: dts: sun7i: Add CAN node
ARM: dts: sun4i: Add can0_pins_a pinctrl settings
ARM: dts: sun4i: Add CAN node
ARM: sun7i: cubietruck: enable ACIN und USB power supply subnode
ARM: dts: sun5i: Add interrupt for display backend
dt-bindings: display: sun4i: Add display backend interrupt to device tree binding
ARM: dts: sun7i: Use axp209.dtsi on A20-OLinuXino-Micro
ARM: dts: sun6i: sina31s: Enable SPDIF out
ARM: sun8i: sina33: add cpu-supply
ARM: sun8i: a33: add all operating points
ARM: sun5i: chip: enable ACIN power supply subnode
ARM: dts: sun8i: sina33: enable ACIN power supply subnode
ARM: dtsi: axp22x: add AC power supply subnode
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Clean-up:
- Add clock/memory nodes
- Add labels for CPU nodes
- Remove unused unit names and reg
- Remove unused skeleton.dtsi
- Add support for PMU
- Add QSPI for sodia board
- Add Reset controller for Arria10
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Merge tag 'socfpga_dts_for_v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.12
- Clean-up:
- Add clock/memory nodes
- Add labels for CPU nodes
- Remove unused unit names and reg
- Remove unused skeleton.dtsi
- Add support for PMU
- Add QSPI for sodia board
- Add Reset controller for Arria10
* tag 'socfpga_dts_for_v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: Add Devkit A10-SR Reset Controller
ARM: dts: socfpga: sodia: enable qspi
ARM: dts: socfpga: Add support for PMU
ARM: dts: socfpga: Add labels for CPU nodes
ARM: dts: socfpga: Do not include skeleton.dtsi
ARM: dts: socfpga: Remove unit name for LEDs in EBV SOCrates
ARM: dts: socfpga: Remove unneeded reg from stmpe_touchscreen
ARM: dts: socfpga: Remove unneeded unit names
ARM: dts: socfpga: Add unit name to memory nodes
ARM: dts: socfpga: Add unit name to clock nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Highlights:
----------
- ADD RTC support on STM32F746 MCU
- Enable RTC on STM32F746 Eval board
- Enable clocks on STM32F746 MCU
- Enable DMA, pwm1 and pwm3 on STM32F429I Eval
- Add support of STM32H743 MCU and his Eval board
- Enable USB HS and FS on STM32F469 Disco board
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Merge tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt
STM32 DT updates for v4.12, round 1
Highlights:
----------
- ADD RTC support on STM32F746 MCU
- Enable RTC on STM32F746 Eval board
- Enable clocks on STM32F746 MCU
- Enable DMA, pwm1 and pwm3 on STM32F429I Eval
- Add support of STM32H743 MCU and his Eval board
- Enable USB HS and FS on STM32F469 Disco board
* tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
dt-bindings: Document the STM32 USB OTG DWC2 core binding
ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco
ARM: dts: stm32: Enable USB FS on stm32f469-disco
ARM: dts: stm32: Add USB FS support for STM32F429 MCU
ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board
ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval
ARM: dts: stm32: Enable dma by default on stm32f4 adc
ARM: dts: stm32: enable RTC on stm32746g-eval
ARM: dts: stm32: Add RTC support for STM32F746 MCU
ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746
dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
ARM: dts: stm32: Enable clocks for STM32F746 MCU
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch fixes the following set of warnings on vexpress platforms:
sysreg@010000 simple-bus unit address format error, expected "10000"
sysctl@020000 simple-bus unit address format error, expected "20000"
i2c@030000 simple-bus unit address format error, expected "30000"
aaci@040000 simple-bus unit address format error, expected "40000"
mmci@050000 simple-bus unit address format error, expected "50000"
kmi@060000 simple-bus unit address format error, expected "60000"
kmi@070000 simple-bus unit address format error, expected "70000"
uart@090000 simple-bus unit address format error, expected "90000"
uart@0a0000 simple-bus unit address format error, expected "a0000"
uart@0b0000 simple-bus unit address format error, expected "b0000"
uart@0c0000 simple-bus unit address format error, expected "c0000"
wdt@0f0000 simple-bus unit address format error, expected "f0000"
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Again, a batch that's been sitting a couple of weeks, mostly because I
anticipated a bit more material but it didn't show up -- which is good.
These are all your garden variety fixes for ARM platforms. Most visible issue
fixed here is probably the SMP reset issue on OMAP, the rest are minor stuff.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Again, a batch that's been sitting a couple of weeks, mostly because
I anticipated a bit more material but it didn't show up -- which is
good.
These are all your garden variety fixes for ARM platforms.
The most visible issue fixed here is probably the SMP reset issue on
OMAP, the rest are minor stuff"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: allwinner: a64: add pmu0 regs for USB PHY
ARM: OMAP2+: omap_device: Sync omap_device and pm_runtime after probe defer
reset: add exported __reset_control_get, return NULL if optional
ARM: orion5x: only call into phylib when available
ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot
ARM: dts: am335x-evmsk: adjust mmc2 param to allow suspend
ARM: dts: ti: fix PCI bus dtc warnings
ARM: dts: am335x-baltos: disable EEE for Atheros 8035 PHY
ARM: dts: OMAP3: Fix MFG ID EEPROM
ARM: sun8i: a33: add operating-points-v2 property to all nodes
ARM: sun8i: a33: remove highest OPP to fix CPU crashes
Without this fix we can get PM related warnings for devices that
use deferred probe. If necessary, this fix can wait for the
v4.12 merge window no problem.
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Merge tag 'omap-for-v4.11/fixes-rc6-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Regression fix for omap interconnect code for deferred probe.
Without this fix we can get PM related warnings for devices that
use deferred probe. If necessary, this fix can wait for the
v4.12 merge window no problem.
* tag 'omap-for-v4.11/fixes-rc6-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: omap_device: Sync omap_device and pm_runtime after probe defer
ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot
ARM: dts: am335x-evmsk: adjust mmc2 param to allow suspend
ARM: dts: ti: fix PCI bus dtc warnings
ARM: dts: am335x-baltos: disable EEE for Atheros 8035 PHY
ARM: dts: OMAP3: Fix MFG ID EEPROM
Signed-off-by: Olof Johansson <olof@lixom.net>
Remove ADC channels that are not available by default on the sama5d3_xplained
board (resistor not populated) in order to not create confusion.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: <stable@vger.kernel.org> # 3.16+
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The voltage reference for the ADC is not 3V but 3.3V since it is connected to
VDDANA.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: <stable@vger.kernel.org> # 3.16+
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The envelope detector can analyze 6 different signals, selectable with a
mux controlled by three gpio pins.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
We found out that HW checksum generation only works from AST2500
onward. This disables it on AST2400 and removes the "no-hw-checksum"
properties in the device-trees. The problem we had wasn't related
to NC-SI.
Also rework the logic testing for that property so it can be used
to disable HW checksum generation and checking regardless of whether
NC-SI is used or not in case other variants out there need this.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
We test for aspeed chips to handle a couple of special cases,
but we do that by checking the machine type which isn't right.
Instead check the actual device compatible property. This also
updates the dtsi files for the aspeed SoC to match.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Recently most nodes got labels to make them referenceable. The USB 3.0
nodes as well as the nodes for the SATA controllers were left out,
rectify the omission.
The labels "sataX" are already used by some boards for the SATA ports,
therefore use "ahciX" to label the SATA controller nodes.
To avoid potential confusion by labeling an USB3.0 controller "usb2" use
usb3_X as labels. This also coincides with the node names themselves
(usb@xxxxx vs usb3@xxxxx).
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the new hdmi phandle to exynos4.dtsi. This phandle is needed by the
s5p-cec driver to initialize the CEC notifier framework.
Tested with my Odroid U3.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: linux-samsung-soc@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
To use CEC notifier sti CEC driver needs to get phandle
of the hdmi device.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
CC: Patrice CHOTARD <patrice.chotard@st.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
The hpd pin of the second hdmi connector of the Utilite Pro is wired
up to a gpio pin of the SoC. Reflect this in the device tree.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On imx6qp-sabresd LDO_ARM is connected to a different PMIC output than
the other imx6qdl-sabresd boards.
Setting cpu0 arm-supply to sw2_reg is wrong, this must have mistakenly
slipped out of the vendor tree where this is are used for LDO bypass.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Setting the supply is optional but beneficial, it will cause PMIC
voltages to be dynamically changed with cpu frequency.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX25 contains two AHB to IP bridges (AIPS), each of which has a set of
control registers. Add the memory regions for the control registers to
the Device Tree.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Model the Carrier Board power distribution by adding a fixed 3.3V
and 5V regulator. The 3.3V regulator is connected to the backlight
as well as the display supply. The 5V regulator is used to supply
USB VBUS.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The ADC is directly supplied by the PMIC 1.8V rail, remove the
superfluous fixed regulator.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The regulator-always-on property on the Ethernet rail prevents Linux
from disabling the rail when Ethernet is shut down (suspend or simply
link down). With this change the regulator framework will disable the
rail when the Ethernet PHY is not used, saving power especially on
carrier board not using Ethernet.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix wrong voltage of PWR_EN_+V3.3 rail. The error had no noticeable
effect since no consumer explicitly requested a specific voltage.
Also use round voltages as it is common in other device trees.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
To make use of the new eLCDIF DRM driver OF graph description is
required. Describe the display using OF graph nodes.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rename the switch2@0 label of the switch2 node to switch@0 to respect
the general unit@address DTS rule, and be consistent with the other
switch nodes of the DTS file.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for i2c nodes i2c1 and i2c2 on Is.IoT MX6UL
eMMC variant boards.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
lcdif nodes are differ wrt specific LCD connected on Is.IoT MX6UL
module, so create separate file 'imx6ul-isiot-common.dtsi' for common
lcdif node structure and include the same on respective dts.
More common nodes will add in future patches.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch add support for lcdif backlight on Is.IoT MX6UL
variant boards.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch add support for lcdif backlight on GEAM6UL
variant boards.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds support for the Zodiac Inflight Innovations RDU2 board,
which has both a Quad and a QuadPlus variant.
The board supports different panels, with the bootloader patching
in the correct compatible, depending on the hardware configuration.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the DT nodes for the Prefetch Resolve Gaskets found on i.MX6QP
and hook them up to the assigned IPU nodes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the DT nodes for the Prefetch Resolve Engines found on i.MX6QP.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The pinfunc definitions are ordered by mux_reg and so automatically by
conf_reg, too. PAD_TDO is the only pad that has a conf_reg but no
mux_reg. Put it to the place where it its in the order of conf_regs
instead of the top.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This was introduced in commit 18e2b50407 ("ARM: dts: imx25-pinfunc:
more defines").
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
System Reset Controller in i.MX7 doesn't have any commonality with IP
block found in i.MX5 and i.MX6 SoC families. Given that and the new
upstream driver for i.MX7 variant (see
https://lkml.org/lkml/2017/2/21/466) remove "fsl,imx51-src" from
compatibility string.
Cc: yurovsky@gmail.com
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus
openframe display carriers" which are good solution for develop
user friendly graphic user interface.
General features:
CPU NXP i.MX6Q rev1.2 at 792 MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
LVDS Display TFT 12.3" industrial, 1280x480 resolution
Backlight LED backlight, brightness 350 Cd/m2
Power supply 15 to 30 Vdc
Cc: Domenico Acri <domenico.acri@engicam.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus
openframe display carriers" which are good solution for develop
user friendly graphic user interface.
General features:
CPU NXP i.MX6Q rev1.2 at 792 MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
LVDS Display TFT 10.1" industrial, 1280x800 resolution
Backlight LED backlight, brightness 350 Cd/m2
Power supply 15 to 30 Vdc
Cc: Domenico Acri <domenico.acri@engicam.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The imx7d-sdb has a mickro bus connector that can be connected to a
Sensirion SHT11 click board (temperature and humidity sensor):
https://shop.mikroe.com/click/sensors/sht1x
Add a new device tree file to describe such hardware.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PHYs embedded in the switch direct there interrupts through the
switch interrupt controllers. Now that devel C has its switch
interrupts connected to the SoC, the PHY interrupts can be used by
phylib. Explicitly include MDIO nodes in the switch device tree nodes,
and link the PHY interrupts back to the switch interrupt
controller. Also, link the ports to the PHYs on the MDIO bus.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The devel B and devel C board use the same GPIO lines for interrupts
from the two switches. Move the pinmux nodes from devel B into the
shared .dtsi file, and wire up the interrupts on devel C.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
UART on i.MX6SX (like all other i.MX6 SoC variants) has the same
programming model as the 'imx6q-uart' type, so add it to the compatible
UART string.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Change the maxium spi clock frequency from 20MHz to 10MHz to meet the
operation voltage range requirement recommended in AT25 datasheet.
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to the reference manuals, both imx50/imx53 SOC seem to share
the same eSDHC controller, especially the section on "Multi-block Read"
mentioned in commit 361b848202 ("mmc: sdhci-esdhc-imx: fix multiblock
reads on i.MX53") is identical for both SOC.
Hence, let imx50 use imx53-esdhc.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Reference them by handle and remove the changed clocks that are copied
from the downstream DT and are not part of the mainline binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Referencing the node by handle make the QP DT more resilent against
changes of the base DT. Also remove the duplicated reg property, it's
not needed as it the same as in the base DT, just the compatible is
actually different.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
By using the handle, we can avoid some duplication of the base DT
and so avoid any maintenance overhead in the QP DT if the referenced
node changes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
All currently supported i.MX25-based machines use phy_type = "utmi" and
dr_mode = "otg". So this seems to be a sensible default.
This also doesn't hurt out-of-tree machines because up to now they had
to specify these two properties in the machine.dts which still takes
precedence by just overwriting the defaults added here.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This machine is based on I2SE's Duckbill 2 board and is sold as part
of I2SE's PLC Bundle for IoT. This is a development kit for Homeplug
Green PHY based powerline products based on Qualcomms QCA7000 chip.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This machine is based on I2SE's Duckbill 2 board and features a
EnOcean daugther board based on the popular TCM310 chipset.
This product is intended to be used for e.g. home automation purposes.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This machine is based on I2SE's Duckbill 2 board and features a
RS-485 daugther board. This device is intended to be used for
e.g. home automation purposes.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This machine is an USB pen drive sized development board,
based on NXP's i.MX28 CPU. In contrast to the previous
model "Duckbill", the "Duckbill 2" series has internal
eMMC storage.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Two fixes for the recent A33 cpufreq support, and one to fix a missing
register in the A64 USB PHY node.
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Merge tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Allwinner fixes for 4.11, bis
Two fixes for the recent A33 cpufreq support, and one to fix a missing
register in the A64 USB PHY node.
* tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: add pmu0 regs for USB PHY
ARM: sun8i: a33: add operating-points-v2 property to all nodes
ARM: sun8i: a33: remove highest OPP to fix CPU crashes
Signed-off-by: Olof Johansson <olof@lixom.net>
The clocksource and the sched_clock provided by the arm_global_timer
are quite unstable because their rates depend on the cpu frequency.
On the other side, the arm_global_timer has a higher rating than the
rockchip_timer, it will be selected by default by the time framework
while we want to use the stable rockchip clocksource.
Let's disable the arm_global_timer in order to have the rockchip
clocksource selected by default.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
The patch add two timers to all rk3188 based boards.
The first timer is from alive subsystem and it act as a backup
for the local timers at sleep time. It act the same as other
SoC rockchip timers already present in kernel.
The second timer is from CPU subsystem and act as replacement
for the arm-global-timer clocksource and sched clock. It run
at stable frequency 24MHz.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
to match devicetree bindings.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Suggested-by: Heiko Stübner <heiko@sntech.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Romulus has a RS-232 connection on the back of chassis, add UART1 to use
this connection.
Signed-off-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The string was changed when upstreaming the driver. Put the correct
string for generation 4 and 5 systems, as well as fix the reg length for
ast2500 systems.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
All chips on OpenPOWER platforms support the fastread SPI command.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Romulus systems have one MX25L25635 (32768 Kbytes) flash module for
the BMC firmware and other MT25QL512A (65536 Kbytes) for the host.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
We do not yet have a clk driver upstream. So that users can boot the
unmodified upstream kernel, add fixed-clock and clock-frequency
properties to all of the clocks.
The values are taken from the Palmetto system. This is the only upstream
dts. It also happens to match all of the systems seen so far.
Acked-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
We do not yet have a clk driver upstream. So that users can boot the
unmodified upstream kernel, add fixed-clock and clock-frequency
properties to all of the clocks.
The values are taken from the ast2500evb. This is the only upstream dts.
It also happens to match all of the systems I have seen so far.
Acked-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This reverts commit 769907ae6e.
This change caused issues with people using USB gadget for serial
consoles. In addition, with the other USB changes coming in, it
makes sense to revert this patch and apply the new set as it
becomes ready.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.
Following interfaces and devices are available on the PCM-947 carrier board:
- 2x UART
- micro SDMMC
- USB host and USB otg
- USB 3503 HSIC hub
- Ethernet
- 2nd alternative KSZ9031 ethernet phy
- Display connectors: PHYTEC LVDS, DDG LVDS, parallel signals, HDMI
- Parallel Camera CIF
- SGTL5000-32QFN audio codec
- 4x LEDs connected via PCA9533
- 2 user buttons
- Expansion connectors for WiFi and other modules
- RTC RV-4162-C7
- Resistive touch STMPE811
- EEPROM M24C32
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:
- 1 GB DDR3 RAM (2 Banks)
- 1x 4 KB EEPROM
- DP83867 Gigabit Ethernet PHY
- 16 MB SPI Flash
- 4 GB eMMC Flash
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero and enable the realtime clock.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit a4ee7e18d8 ("ARM: dts: armada: Add default trigger for sata
led") adds the default trigger to individual boards, move it to
armada-385-linksys.dtsi which effectively enables the definition for
the WRT1900ACS (Shelby) as well as for future boards.
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add CRC (CRC32 crypto) support to stm32f746.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx
SinA33 has its cpu-supply property set in the cpu DT node.
Therefore, CPUfreq knows how to handle the regulator in charge of the
CPU and can adjust its voltage to match the OPP.
Add these two CPU frequencies to the CPU OPP table of the Sinlinx
SinA33.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds GPU thermal throttling for the Allwinner A33.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
This adds CPU thermal throttling for the Allwinner A33. It uses the
thermal sensor present in the SoC's GPADC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds the DT node for the thermal sensor present in the Allwinner
A33 GPADC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch changes the device node position of ps20 and ps21 to fix
ordering by rising physical address.
From
uart7: serial@01c29c00
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
ps20: ps2@01c2a000
ps21: ps2@01c2a400
to
uart7: serial@01c29c00
ps20: ps2@01c2a000
ps21: ps2@01c2a400
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the RTC clocks to device tree. The frequencies must be fixed values
according to the hardware manual.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The X2 crystal oscillator on the Koelsch development board provides a
74.25 MHz clock, not a 148.5 MHz clock.
Fixes: cd21cb46e1 ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
I disabled SRAM and GPMC originally when seeing errors with
omap_barriers_init(). But that is no longer happening probably
because the memory range is now properly configured to 1021 MB
instead of 1024 MB. So let's enable SRAM and GPMC so we get
omap_barriers_init() working and can idle the GPMC.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The CPCAP PMIC interrupt is level high sensitive despite it being
requested as edge high triggered in the Motorola Linux kernel.
Note that also the related driver change is needed posted as
"mfd: cpcap: Fix interrupt to use level interrupt".
Fixes: 56e1d40d3b ("mfd: cpcap: Add minimal support")
Cc: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the 2 ethernet ports as CPSW ports in dual-mac mode
Signed-off-by: Roger Quadros <rogerq@ti.com>
[nsekhar@ti.com: use AM33XX_IOPAD()]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM571x IDK and the AM572x IDK use CAN1 interface.
This patch enables it for both boards.
Tested on AM572x IDK using cansequence.
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[nsekhar@ti.com: move to use DRA7XX_CORE_IOPAD())
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two
H3 boards and one H5 board.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 SoC has an on-board CAN controller. This patch adds
the pinctrl settings for pins PH20 and PH21.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 SoC has an on-board CAN controller.
This patch adds the device node.
The CAN controller is inherited from the A10 SoC and uses the same driver.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10 SoC has an on-board CAN controller. This patch adds the
pinctrl settings for pins PH20 and PH21.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10 SoC has an on-board CAN controller.
This patch adds the device node.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Cubietruck has an AXP209 PMIC and can be power-supplied by ACIN via
the CHG-IN pin or by USB.
This enables the ACIN and the USB power supply subnode in the DT.
Signed-off-by: Alexander Syring <alex@asyring.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: 072d326542 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: ee9141522d ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: bcde372254 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not
the 33MHz Peripheral 0 (P0) clock.
Fixes: 969244f9c7 ("ARM: dts: r7s72100: add ethernet clock to device tree")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables USB HS working in FS mode on stm32f429-disco
with 5V VBUS enable.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch enables USB FS on stm32f469-disco with 5V VBUS enable.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch adds the USB pins and nodes for USB FS core.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Update the Alpine clock-frequency values with valid default values. The
bootloader can still update these values if needed, but at least we can
boot if it does not.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Cosmetic cleanup to have consistent node definitions. Add a space before
the node units which do not have one.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
At this time, most of changes are for ASoC, while we got one fix for
yet another race of ALSA sequencer core and a usual HD-audio quirk.
The ASoC changes are mostly small and device-specific fixes. A
slightly large volume is seen in sun8i-codec, which is a new code in
4.11, and we'd like to fix user-visible stuff before the official 4.1
release.
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Merge tag 'sound-4.11-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound fixes from Takashi Iwai:
"At this time, most of changes are for ASoC, while we got one fix for
yet another race of ALSA sequencer core and a usual HD-audio quirk.
The ASoC changes are mostly small and device-specific fixes. A
slightly large volume is seen in sun8i-codec, which is a new code in
4.11, and we'd like to fix user-visible stuff before the official 4.1
release"
* tag 'sound-4.11-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (27 commits)
ALSA: hda - fix a problem for lineout on a Dell AIO machine
ASoC: simple-card: fix simple_dai clk lookup
ASoC: STI: Fix reader substream pointer set
ALSA: seq: Fix race during FIFO resize
ARM: dts: sun8i: Update audio-routing with renamed widgets
ASoC: sun8i-codec: Convert to use SND_SOC_DAPM_AIF_IN
ASoC: sun8i-codec: Fix space on audio-routing widget
ASoC: sun8i-codec: Update mixer to use SOC_DAPM_DOUBLE
ASoC: sun8i-codec: Remove analog "HP" widget
ASoC: rt5665: fix wrong shift rt5665_if2_1_adc_in_enum
ASoC: rt5665: fix define of RT5665_HP_DRIVER_5X
ASoC: rcar: dma: remove unnecessary "volatile"
ASoC: rcar: clear DE bit only in PDMACHCR when it stops
ASoC: rsnd: fix sound route path when using SRC6/SRC9
ASoC: don't dereference NULL pcm_{new,free}
ASoC: rt5665: CLKDET is also a power of ASRC
ASoC: rt5665: Vref3 is necessary for Mono Amp
ASoC: rt5665: increase LDO level
ASoC: rt5665: fix getting wrong work handler container
ASoC: atmel-classd: fix audio clock rate
...
There was a little conflict between the v4.11 bugfixes and the new changes for 4.12,
this merges the fixes into the 4.12 branch to avoid having to resolve it again.
* Broadcom fixes in mainline
ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
ARM: dts: BCM5301X: Fix memory start address
ARM: dts: BCM5301X: Fix UARTs on bcm953012k
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add hecc node for am35x
- Add onenand support for omap3-igep
- Add bluetooth binding for n900/n9/n950
- Configure clocks and SATA for dm81xx
- Update operating points tables for am33xx, am43xx and dra7
- Update SPI flash documentation for w25q64
- Configure SPI NOR for am335x-icev2
- Mux uart0 for am437x-gp-evm
- Add thermal zones for omap3, omap4, omap5, dra7
- Configure LEDs for am335x-baltos
- A series of droid 4 changes to configure various devices
such as keypad, regulators, gpio-keys, rtc, power button,
compass, accelerometer, touchscreen, backlight, poweroff,
tmp105, HDMI, LCD panel and LEDs, EHCI, and micro-SD
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Merge tag 'omap-for-v4.12/dt-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Devicetree changes for omaps for v4.12 merge window" from Tony Lindgren:
- Add hecc node for am35x
- Add onenand support for omap3-igep
- Add bluetooth binding for n900/n9/n950
- Configure clocks and SATA for dm81xx
- Update operating points tables for am33xx, am43xx and dra7
- Update SPI flash documentation for w25q64
- Configure SPI NOR for am335x-icev2
- Mux uart0 for am437x-gp-evm
- Add thermal zones for omap3, omap4, omap5, dra7
- Configure LEDs for am335x-baltos
- A series of droid 4 changes to configure various devices
such as keypad, regulators, gpio-keys, rtc, power button,
compass, accelerometer, touchscreen, backlight, poweroff,
tmp105, HDMI, LCD panel and LEDs, EHCI, and micro-SD
* tag 'omap-for-v4.12/dt-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (35 commits)
ARM: dts: am335x-baltos: add LED support
ARM: dts: omap4-droid4: Fix MMC1 card for detect GPIO and regulator
ARM: dts: OMAP4460: Thermal: Add slope and offset values
ARM: dts: OMAP443x: Thermal: Add slope and offset values
ARM: dts: OMAP5: Thermal: Add slope and offset values
ARM: dts: DRA7: Thermal: Add slope and offset values
ARM: dts: omap3: Add cpu_thermal zone
ARM: dts: am437x-gp-evm: Add pinmux for uart0
ARM: dts: am335x-icev2: Add SPI based NOR
Documentation: devicetree: mtd: add w25q64 to list of supported SPI flashes
ARM: dts: dra7: Add updated operating-points-v2 table for cpu
ARM: dts: am4372: Update operating-points-v2 table for cpu
ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu
ARM: dts: am33xx: Add updated operating-points-v2 table for cpu
ARM: dts: dm8168-evm: add SATA node
ARM: dts: dm8168-evm: add the external reference clock for SATA
ARM: dts: N9/N950: add bluetooth
ARM: dts: N900: Add bluetooth
ARM: dts: omap4-droid4: Configure EHCI so modems can be accessed
ARM: dts: motorola-cpcap-mapphone: add LEDs
...
definitions for the mmc resets in the socs reset controller, sound
support for the Rock2, dma support for mmc controllers on the rk3188
and a led-fix for the MiQi board and and irq-fix for older Cortex-A9 socs.
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Merge tag 'v4.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "Rockchip dts32 updates for 4.12 part1" from Heiko Stübner:
Contains one new board, the Tinkerboard from Asus based on the rk3288,
definitions for the mmc resets in the socs reset controller, sound
support for the Rock2, dma support for mmc controllers on the rk3188
and a led-fix for the MiQi board and and irq-fix for older Cortex-A9 socs.
* tag 'v4.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: setup DMA-channels for mmc0 and emmc for rk3188
ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs
ARM: dts: rockchip: add rk322x dw-mmc resets
ARM: dts: rockchip: add rk3066/rk3188 dw-mmc resets
ARM: dts: rockchip: add rk3036 dw-mmc resets
ARM: dts: rockchip: add rk3288 dw-mmc resets
ARM: dts: rockchip: add dts for RK3288-Tinker board
dt-bindings: add rk3288-based Asus Tinker board
ARM: dts: rockchip: fix the MiQi board's LED definition
ARM: dts: rockchip: Add support for ES8388 to the Radxa Rock 2
- Add the power controller to the DTS.
- Augment the GPIO nodes to also include the Faraday
compatible.
- Add the PCI bus host and config to the Gemini device trees.
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Merge tag 'gemini-dts-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
Pull "DTS updates for the Gemini on top of the multiplatform base" from Linus Walleij:
- Add the power controller to the DTS.
- Augment the GPIO nodes to also include the Faraday
compatible.
- Add the PCI bus host and config to the Gemini device trees.
* tag 'gemini-dts-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: add PCI to the Gemini device trees
ARM: dts: augment Gemini GPIO nodes
ARM: dts: add power controller to the Gemini DTS
4.12, please pull the following:
- Rafal:
* adds basic support for the Linksys EA9200, Linksys EA6300 V1, Linksys
EA9500, TP-Link Archer C5 V2 which are all based on BCM470x SoCs with
a bunch of BCM43602 radios.
* updates the BCM5301X DTS and DTS include file and moves the serial
console parameters to the DTS include file since all BCM5301X that we have so
far are consistent in using the same UART. He also does the same for the
BCM53573 DTS.
* makes some updates to the Tenda AC9 platform by describing its
PCIe controllers and endpoints in order to be able to represent GPIOs attached
to the on-chip Wi-Fi module. Once done, he adds the 2Ghz LED which is connected
to one of these GPIOs.
* re-licenses the DTS files he created to the ISC license
* removes the use of the non-existend "default-off" LED trigger in the
BCM53573 and BCM5301X DTS files
- Aditya adds missing Netgear R8000 LEDS and keys for WAN status LEDS and brightness
- Jon:
* adds NAND controller Device Tree nodes to the BCM953012K reference board
* converts the BCM5301X SoC to use the recently introduced Broadcom QSPI controller
Device Tree nodes.
* fixes the GIC PPI interrupt flags that the kernel now
reports about.
* adds ARM TWD watchdog entries to the BCM5301X DTS include file
* adds I2C entries to the BCM5301X DTS include files.
* disables i2c by default in the Northstar Plus DTS include file, and
,enables it at the board level instead.
* adds USB (OHCI & EHCI) Device Tree nodes to the Northstar Plus DTS
include files.
- Steven adds the mailbox (PDC) unit and the crytographic unit (SPU) to the
Broadcom Northstar Plus SoC DTS include file. Steven also adds proper ethernet
aliases to the BCM53012HR board since some bootloaders require that for MAC address
patching.
- Eric adds the DSI and its corresponding clock nodes to the BCM283x DTS files
but leaves them disabled by default (overlays should take care of enabling it)
- Boris adds support for HDMI audio and related DMA channels to the BCM283x SoCs
- Gerd adds support for the BCM2835 specific SDHCI controller to the BCM283x SoCs
- Rob fixes the iProc msi-controller name and unit address now that DTC can produce
additional errors
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Merge tag 'arm-soc/for-4.12/devicetree' of http://github.com/Broadcom/stblinux into next/dt
Pull "Broadcom devicetree changes for 4.12" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoCs Device Tree updates for
4.12, please pull the following:
- Rafal:
* adds basic support for the Linksys EA9200, Linksys EA6300 V1, Linksys
EA9500, TP-Link Archer C5 V2 which are all based on BCM470x SoCs with
a bunch of BCM43602 radios.
* updates the BCM5301X DTS and DTS include file and moves the serial
console parameters to the DTS include file since all BCM5301X that we have so
far are consistent in using the same UART. He also does the same for the
BCM53573 DTS.
* makes some updates to the Tenda AC9 platform by describing its
PCIe controllers and endpoints in order to be able to represent GPIOs attached
to the on-chip Wi-Fi module. Once done, he adds the 2Ghz LED which is connected
to one of these GPIOs.
* re-licenses the DTS files he created to the ISC license
* removes the use of the non-existend "default-off" LED trigger in the
BCM53573 and BCM5301X DTS files
- Aditya adds missing Netgear R8000 LEDS and keys for WAN status LEDS and brightness
- Jon:
* adds NAND controller Device Tree nodes to the BCM953012K reference board
* converts the BCM5301X SoC to use the recently introduced Broadcom QSPI controller
Device Tree nodes.
* fixes the GIC PPI interrupt flags that the kernel now
reports about.
* adds ARM TWD watchdog entries to the BCM5301X DTS include file
* adds I2C entries to the BCM5301X DTS include files.
* disables i2c by default in the Northstar Plus DTS include file, and
,enables it at the board level instead.
* adds USB (OHCI & EHCI) Device Tree nodes to the Northstar Plus DTS
include files.
- Steven adds the mailbox (PDC) unit and the crytographic unit (SPU) to the
Broadcom Northstar Plus SoC DTS include file. Steven also adds proper ethernet
aliases to the BCM53012HR board since some bootloaders require that for MAC address
patching.
- Eric adds the DSI and its corresponding clock nodes to the BCM283x DTS files
but leaves them disabled by default (overlays should take care of enabling it)
- Boris adds support for HDMI audio and related DMA channels to the BCM283x SoCs
- Gerd adds support for the BCM2835 specific SDHCI controller to the BCM283x SoCs
- Rob fixes the iProc msi-controller name and unit address now that DTC can produce
additional errors
* tag 'arm-soc/for-4.12/devicetree' of http://github.com/Broadcom/stblinux: (27 commits)
ARM: dts: bcm: fix msi-controller name and unit address
ARM: dts: BCM53573: Specify serial console parameters
ARM: dts: BCM5301X: Specify serial console params in dtsi files
ARM: dts: NSP: Add crypto (SPU) to dtsi
ARM: dts: NSP: Add mailbox (PDC) to NSP
ARM: dts: BCM953012HR: Add ethernet aliases
ARM: dts: BCM5301X: Add support for TP-LINK Archer C5 V2
ARM: dts: NSP: disable i2c DT entry by default
ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree
ARM: dts: BCM5301X: Add I2C support to the DT
ARM: dts: BCM5301X: Add TWD WD Support to DT
ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
ARM: dts: bcm2835: add sdhost controller to devicetree
ARM: dts: bcm283x: Add HDMI audio related properties
ARM: dts: BCM5301X: Don't use nonexistent "default-off" LED trigger
ARM: dts: BCM53573: Don't use nonexistent "default-off" LED trigger
ARM: dts: BCM5301X: Add missing Netgear R8000 LEDs and Keys
ARM: dts: BCM5301X: Relicense DTS files I created to the ISC
ARM: dts: bcm2835: Add the DSI module nodes and clocks.
ARM: dts: BCM53573: Add Tenda AC9 2 GHz LED
...
- Add node lable for Armada 38x
- Add support for Synology DS116 NAS and Linksys WRT1900ACS
- Update mbus controller description on Armada 38x allowing entering in standby
- Add default trigger for sata led on various linksys boards
- Update newly added armada-xp-98dx3236
- Enable hardware buffer manager support for the devices in the
Linksys WRT AC Serie
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Merge tag 'mvebu-dt-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt for 4.12 (part 1)" from Gregory CLEMENT:
- Add node lable for Armada 38x
- Add support for Synology DS116 NAS and Linksys WRT1900ACS
- Update mbus controller description on Armada 38x allowing entering in standby
- Add default trigger for sata led on various linksys boards
- Update newly added armada-xp-98dx3236
- Enable hardware buffer manager support for the devices in the
Linksys WRT AC Serie
* tag 'mvebu-dt-4.12-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: mvebu: linksys: enable buffer manager support
ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236
ARM: dts: mvebu: Move mv98dx3236 clock bindings
ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
ARM: dts: armada-xp-98dx3236: combine dfx server nodes
ARM: dts: armada: Add default trigger for sata led
ARM: dts: armada-38x: Adjust mbus controller description on Armada 38x
ARM: dts: armada-385: add support for the Linksys WRT1900ACS (Shelby)
ARM: dts: armada-385-synology-ds116: add support for Synology DS116 NAS
ARM: dts: armada-38x add node labels
Video display on DA850 along with some
whitespace clean-up.
Also, enables sound and ADC support on
Lego EV3.
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Merge tag 'davinci-for-v4.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt
Pull "DaVinci DT updates for v4.12" from Sekhar Nori:
DaVinci device tree updates to enable
Video display on DA850 along with some
whitespace clean-up.
Also, enables sound and ADC support on
Lego EV3.
* tag 'davinci-for-v4.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-evm: add the output port to the vpif node
ARM: dts: da850-evm: add IO expander node on UI card
ARM: dts: da850: add vpif video display pins
ARM: dts: da850-evm: fix whitespace errors
ARM: da850-lego-ev3: Add device tree node for sound
ARM: da850-lego-ev3: Add device tree node for A/DC
The Moxa ART GPIO is a Faraday FTGPIO010. Augment the DTS node
to indicate both compatible values for the SoC and the IP part.
Also increase the register range to 0x100, it has at least 0x48
bytes of registers, and a few extra will not hurt.
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the new hdmi phandle to exynos4.dtsi. This phandle is needed by the
s5p-cec driver to initialize the CEC notifier framework.
Tested with my Odroid U3.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Keep the clearfog DTS file ordered alphabetically - Florian placed the
MDIO entry after pinctrl, which mis-orders the file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This moves the spi0_cs3_pin pinconf node from the LEGO EV3 file to the
common DA850 include file. This node is applicable to any board, and
therefore belongs in the common file.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The two st231-rproc nodes have the same name; Due to that it was
impossible to distinguish them in remoteproc sysfs and debugfs
interface.
This patch provides them a name related to their functionality.
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
The display backend on sun5i shares the same interrupt line as the
display frontend. Add it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the RPM Clock Controller DT node for msm8974-based platforms, so that
drivers can use the clocks provided by the RPM processor.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The DTS referred to SDC5 when it meant SDC1.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
To make the picture complete, add DTS entries also for the
second and fourth MMC/SD blocks on the MSM8660. SDC2 is
an 8-bit interface and SDC4 is a 4-bit interface.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Without this patch (and with CONFIG_QCOM_ADSP_PIL), I get this error:
[ 0.711529] qcom_adsp_pil adsp-pil: failed to get xo clock
[ 0.711540] remoteproc remoteproc0: releasing adsp-pil
With this patch, adsp-pil can initialize correctly.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add initial set of CoreSight components found on Qualcomm
msm8974 and apq8074 based platforms, including the APQ8074
Dragonboard board.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The Rock 2 square board has a USB -> SATA converter hooked up to its usb
host1 connection. Enable the usb controller and always turn on the power
on the 5V sata power connector (controlled by gpio).
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
All three devices provide GPIO based LEDs named power,
wlan and app.
Place LEDs definition into a separate dtsi file as not all
devices including am335x-baltos.dtsi have the same LED layout.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There's a typo, it should be GPIO176 and not GPIO106.
And it seems I messed up the regulators at some point while trying
to figure out what devices the regulators are used. The correct
regulator for MMC1 is vwlan2.
Fixes: 0d4cb3ccee ("ARM: dts: Configure regulators for droid 4")
Reported-by: Sebastian Reichel <sre@kernel.org>
Reviewed-by: Sebastian Reichel <sre@kernel.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 84e734f497 ("ARM: dts: silk: add DU DT support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 876e7fb9f4 ("ARM: shmobile: r8a7794: alt: Enable VGA port")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 46c4f13d04 ("ARM: shmobile: r8a7794: Add DU node to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the missing module clock for the second channel of the display unit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
An alias name should have an index number even when it is the only of its type.
This allows U-Boot to add the local-mac-address property. Otherwise U-Boot
skips the alias.
Fixes: 6a93792774 ("ARM: bcm2835: dt: Add the ethernet to the device trees")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Eric Anholt <eric@anholt.net>
According to the BCM2835 ARM Peripherals document uart1 doesn't map to pins
36-39, but uart0 does.
Also, split into separate Rx/Tx and CST/RTS groups to match other uart nodes.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Eric Anholt <eric@anholt.net>
According to the BCM2835 ARM Peripherals document i2c0 doesn't map to pins 32,
34 but to 28, 29.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Eric Anholt <eric@anholt.net>
Downstream kernel uses pins 32, 33 as UART0 (PL011) Rx/Tx to communicate with
the Bluetooth chip. So ALT3 of these pins is most likely not CTS/RTS. Change
the node name to reflect that. This matches section 6.2 "Alternative Function
Assignments" in the BCM2835 ARM Peripherals document.
With this change in place, adding
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
};
to bcm2837-rpi-3-b.dts does the right thing on my Raspberry Pi 3.
Pins 30, 31 are CTS/RTS of UART0 in alternate function 3. Rename uart0_gpio30
as well.
While at it, fix a little typo in a nearby comment.
Fixes: 21ff843931 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Eric Anholt <eric@anholt.net>
mmc2 used for wl12xx was missing the keep-power-in suspend
parameter. As a result the board couldn't reach suspend state.
Signed-off-by: Eyal Reizer <eyalr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Orange Pi Zero board features a USB OTG port, which has a ID pin, and
can be used to power up the board. However, even if the board is powered
via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot
be powered up, thus it's impossible to use it in host mode with simple
OTG cables.
Add support for it in peripheral mode.
If someone really want to use it in host mode, the mode of PHY can be
switch via sysfs, then use a powered USB OTG cable or powered USB HUB to
power up external USB devices.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Orange Pi One features a MicroUSB port that can work in both host mode
and peripheral mode.
When in host mode, its VBUS is controlled via a GPIO; when in peripheral
mode, its VBUS cannot be used to power up the board.
Add support for this port.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.
Add device nodes for these controllers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
updated. So we should really share almost the whole .dtsi.
In preparation for that move the peripheral parts of the existing
sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi.
The actual sun8i-h3.dtsi then includes that and defines the H3 specific
parts on top of it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: also split out mmc and gic, as well as pio and ccu's
compatible, and make drop of skeleton into a seperated patch]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
According to the datasheets provided by Allwinner, both Allwinner H3 and
H5 use GIC-400 as their interrupt controller.
For better device tree reusing, correct the GIC compatible in H3 DTSI to
"arm,gic-400", thus this node can be reused in H5.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
After converting to generic pinconf binding, pinctrl-a10.h is now not
used at all.
Drop its inclusion for H3 DTSI.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The skeleton.dtsi file is now deprecated, and do not exist in ARM64
environment.
Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64
chip, drop skeleton.dtsi inclusion now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit makes use of the axp209.dtsi file to define the
AXP209 PMIC. While here, define the rails that are enabled on
this board.
Tested checking the regulator voltage varies according to the
CPU frequency.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The SinA31s has a coaxial SPDIF output. Enable it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds the cpu-supply DT property to the cpu0 DT node needed by
the board to adapt the regulator voltage depending on the currently used
OPP.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds almost all operating points allowed for the A33 as defined by
fex files available at:
https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33
There are more possible frequencies in this patch than there are in the
fex files because the fex files only give an interval of possible
frequencies for a given voltage. All supported frequencies are defined
in the original driver code in Allwinner vendor tree.
There are two missing frequencies though: 1104MHz and 1200MHz which
require the CPU to have 1.32V supplied, which is higher than the default
voltage.
Without all A33 boards defining the CPU regulator, we cannot have these
two frequencies as it would cause the CPU to try to run a higher
frequency without "overvolting" which is very likely to crash the CPU.
Therefore, these two frequencies must be enabled on a per-board basis.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The NextThing Co. CHIP has an AXP209 PMIC and can be power-supplied by
ACIN via the CHG-IN pin.
This enables the ACIN power supply subnode in the DT.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Sinlinx SinA33 has an AXP223 PMIC and an ACIN connector, thus, we
enable the ACIN power supply in its Device Tree.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The X-Powers AXP22X PMIC exposes the status of AC power supply.
This adds the AC power supply subnode for the AXP22X PMIC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The X-Powers AXP20X PMIC exposes the status of AC power supply, the
current current and voltage supplied to the board by the AC power
supply.
This adds the AC power supply subnode for AXP20X PMIC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All dts files for the sunxi platform have been switched to the generic
pinconf bindings. As a result, the sunxi specific pinctrl macros are
no longer used.
Remove the #include entry with the following command:
sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \
arch/arm/boot/dts/sun?i*.*
arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra
empty line.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The old sunxi specific pinctrl bindings are deprecated, in favor of
the new generic pinconf bindings. Also, we are moving towards handling
GPIO pinmux settings that don't require extra bias or drive strength
settings to use the GPIO bindings only.
This patch removes the last instance of the sunxi specific pinctrl
bindings that use the pinctrl header by dropping the pinmux setting
for the audio codec's PA (external amplifier) control GPIO. The pin
is pulled down externally.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
PCIe bridges should have a node name of 'pcie'.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
The Cortina Gemini has an internal PCI root bus, add this to
the device tree, and add interrupt mapping (swizzling) to the
relevant systems device trees.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Feng-Hsin Chiang <john453@faraday-tech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Raspberry Pi, and nodes to describe the DSI and SDHOST hardware
modules (which are still disabled by default).
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Merge tag 'bcm2835-dt-next-2017-03-21' into devicetree/next
This pull request brings in the DT nodes for enabling HDMI audio on
Raspberry Pi, and nodes to describe the DSI and SDHOST hardware
modules (which are still disabled by default).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
please pull the following:
- Jon fixes a reboot issue on most Northstar Plus platforms by adding the
"open-source" property to the "gpio-restart" Device Tree nodes
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Merge tag 'arm-soc/for-4.11/devicetree-fixes-2' of http://github.com/Broadcom/stblinux into fixes
Pull "Broadcom arm Device Tree fixes for 4.11 (part 2)" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoCs Device Tree fixes for 4.11,
please pull the following:
- Jon fixes a reboot issue on most Northstar Plus platforms by adding the
"open-source" property to the "gpio-restart" Device Tree nodes
* tag 'arm-soc/for-4.11/devicetree-fixes-2' of http://github.com/Broadcom/stblinux:
ARM: dts: NSP: GPIO reboot open-source
Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add basic support for STM32H743 MCU and his eval board.
The STMicrolectornics's STM32H743 MCU is based on Cortex-M7 core
running up to @400MHz with 2MB internal flash and 1MB internal RAM.
For more details see:
Documentation/arm/stm32/stm32h743-overview.txt
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Add pinmux for rx,tx,cts and rts lines of uart0. This will enable uart0
to use hardware flow control.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable support for W25Q64CVSSIG which is a Winbond 64 Mbit SPI NOR.
At boot you will see the following message:
m25p80 spi1.0: found s25fl064k, expected w25q64
This is because the JEDEC ID for this chip is the same as s25fl064k.
However, this should be harmless since both chips are essentially the
same.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After the ti-cpufreq driver has been added, we can now drop the
operating-points table present in dra7.dtsi for the cpu and add an
operating-points-v2 table with all OPPs available for all silicon
revisions. Also add necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime as part of the operating-points
table.
As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.
Information from SPRS953, Revised December 2015.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
eviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The operatings-points-v2 table for am4372 was merged before any user of
it was present in the kernel and before the binding had been finalized.
The new ti-cpufreq driver and binding expects the platform specific
properties to be part of the operating-points-v2 table rather than the
cpu node so let's move them there as the only user is the ti-cpufreq
driver.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
eviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Although all PG2.0 silicon may not support 1GHz OPP for the MPU, older
Beaglebone Blacks may have PG2.0 silicon populated and these particular
parts are guaranteed to support the OPP, so enable it for PG2.0 on
am335x-boneblack only.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
eviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After the ti-cpufreq driver has been added, we can now drop the
operating-points table present in am33xx.dtsi for the cpu and add an
operating-points-v2 table with all OPPs available for all silicon
revisions. Also add necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime as part of the operating-points
table.
Information from AM335x Data Manual, SPRS717i, Revised December 2015,
Table 5-7.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
eviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the SATA controller node to the dm8168-evm device tree.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This board has an external oscillator supplying the reference clock
signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
device tree node.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Though cpsw doesn't support EEE feature, Atheros 8035 provides
automatic EEE support that is enabled by default. This causes
occasional link drops when link partner also announces EEE support.
These link drops occur on both 100Mbit/s and 1000Mbit/s speeds.
So disable EEE advertising completely.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The manufacturing information is stored in the EEPROM. This chip
is an AT24C64 not not (nor has it ever been) 24C02. This patch will
correctly address the EEPROM to read the entire contents and not just
256 bytes (of 0xff).
Fixes: 5e3447a29a ("ARM: dts: LogicPD Torpedo: Add AT24 EEPROM Support")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch set HSE_RTC clock frequency to 1 MHz, as the clock supplied to
the RTC must be 1 MHz.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch lists STM32F7's RCC numeric constants.
It will be used by clock and reset drivers, and DT bindings.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch enables clocks for STM32F746 MCU.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Add appropriate properties to devices in the Linksys WRT AC Series for the
mvneta driver to use hardware buffer management.
Also update "soc" ranges property and set the status of bm and bm-bppi
to "okay" (SRAM).
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[adapted rk1108 dtsi to keep bisectability]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Nokia N950 and N9 have a wl1271 (with nokia bootloader) bluetooth
module connected to second UART.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add bcm2048 node and its system clock to the N900 device tree file.
Apart from that a reference to the new clock has been added to
wl1251 (which uses it, too).
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The unit address for the msi controller is not valid as there is no reg
property, so remove it. Also, msi-controller is the preferred node name.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Acked-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[include rename in rk1108.dtsi to prevent compile errors]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds baud rate, parity & number of data bits. It's required to get
serial working correctly.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
So far every Northstar device we have seen was using the same serial
console params (115200n8). It probably make the most sense to put it in
some proper dtsi files instead of repeating over and over for every
single device. As different boards may use different bootloaders it
seems the safest idea is to use board specific dtsi files.
Just in case some vendor decides to use different UART (parameters) this
can be always easily overwritten.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Droid 4 has two modems, mdm6600 and w3glte. Both are on the HCI USB
controller.
Let's add a configuration for the HCI so the modems can be enabled.
Note that the modems still need additional GPIO based configuration.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
[tony@atomide.com: left out url]
Signed-off-by: Tony Lindgren <tony@atomide.com>
The LCD panel on droid 4 is a command mode LCD. The binding follows
the standard omapdrm binding and the changes needed for omapdrm command
mode panels are posted separately.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can get HDMI working as long as the 5V regulator is on. There is
probably an encoder chip there too, but so far no idea what it might be.
Let's keep the 5V HDMI regulator always enabled for now as otherwise we
cannot detect the monitor properly.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add tmp105 sensor for droid 4. This can be used with modprobe
lm75.ko and running sensors from lm-sensors package. Note that
the lm75.c driver does not yet support alert interrupt but
droid 4 seems to be wired for it.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Tested-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Droid 4 has a GPIO line that we can use with CONFIG_POWER_RESET_GPIO.
It is probably connected to the CPCAP PMIC, and seems to power down
the whole device taking power consumption to zero based on what
I measured.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Tested-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The TI LMU driver has not yet been merged, but the device
tree binding for TI LMU drivers has been acked already
earlier by Rob Herring <robh+dt@kernel.org>. So it should
be safe to apply to cut down the number of pending patches.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: Milo Kim <milo.kim@ti.com>
Tested-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit enable DMA-based transfers for SD/eMMC card adapters
and reduce number of interrupts produced by SD-card/eMMC-card
adapters.
Sometimes interrupts from SD-card/eMMC-card adapters running in
PIO mode blocks execution of hrtimers and I2S DMA callbacks for
a long periods (100 ms or more).
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
[moved dma properties to rk3xxx.dtsi and added sdio dma]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The binding should state "cortina,gemini-gpio", "faraday,ftgpio010"
stating the full name of the IP part.
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to [0] pointed out by Marc Zyngier in a report about a
similar error message, PPIs 11 and 13 are edge triggered on
Cortex-A9 socs including the rk3066 and rk3188 which currently
mark them as level triggered.
Until some time ago the gic did not care but commit 992345a58e
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
introduced a warning for that case.
Fix the warning on these socs by describing the interrupts correctly
and also using the binding constants for easier reading in the future.
[0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The OPP are declared as shared but no operating points are declared for
cpu1, 2 and 3. Thus, the following error happens during the boot:
cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find tcpu_dev node.
This patch applies the operating points to each cpu of the A33.
Fixes: 03749eb88e ("ARM: dts: sun8i: add opp-v2 table for A33")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC
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Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.12
Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC
* tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
ARM: dts: silk: Drop superfluous status update for frequency override
ARM: dts: alt: Drop superfluous status update for frequency override
ARM: dts: gose: Drop superfluous status update for frequency override
ARM: dts: porter: Drop superfluous status update for frequency override
ARM: dts: koelsch: Drop superfluous status updates for frequency overrides
ARM: dts: lager: Drop superfluous status update for frequency override
ARM: dts: marzen: Drop superfluous status update for frequency override
ARM: dts: bockw: Drop superfluous status update for frequency override
ARM: dts: porter: Always use status "okay" to enable devices
ARM: dts: r8a7793: Add INTC-SYS clock to device tree
ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Add INTC-SYS clock to device tree
ARM: dts: r8a7792: Add INTC-SYS clock to device tree
ARM: dts: r8a7791: Add INTC-SYS clock to device tree
ARM: dts: r8a7790: Add INTC-SYS clock to device tree
ARM: dts: r8a73a4: Add INTC-SYS clock to device tree
ARM: dts: r7s72100: Add watchdog timer
ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fix USB host for sama5d2
- Fix cpuidle on sama5
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Merge tag 'at91-ab-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into fixes
Fixes for 4.11:
- Fix USB host for sama5d2
- Fix cpuidle on sama5
* tag 'at91-ab-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: at91: pm: cpu_idle: switch DDR to power-down mode
Revert "ARM: at91/dt: sama5d2: Use new compatible for ohci node"
Signed-off-by: Olof Johansson <olof@lixom.net>
A bunch of device tree fixes for various boards / SoCs.
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Merge tag 'sunxi-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Allwinner fixes for 4.11
A bunch of device tree fixes for various boards / SoCs.
* tag 'sunxi-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sun8i: a23/a33: drop bl_en_pin GPIO pinmux in reference design DTSI
ARM: dts: sun7i: lamobo-r1: Fix CPU port RGMII settings
ARM: sun8i: Fix the mali clock rate
Signed-off-by: Olof Johansson <olof@lixom.net>
- A fix to reboot hang seen on imx6sx-udoo-neo board, by removing
arm-supply and soc-supply and using LDO enabled mode.
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Merge tag 'imx-fixes-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.11:
- A fix to reboot hang seen on imx6sx-udoo-neo board, by removing
arm-supply and soc-supply and using LDO enabled mode.
* tag 'imx-fixes-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6sx-udoo-neo: Fix reboot hang
Signed-off-by: Olof Johansson <olof@lixom.net>
The moxart interrupt line flags were not respected in previous
driver: instead of assigning them per-consumer, a fixes mask
was set in the controller.
With the migration to a standard Faraday driver we need to
set up and handle the consumer flags correctly. Also remove
the Moxart-specific flags when switching to using real consumer
flags.
Extend the register window to 0x100 bytes as we may have a few
more registers in there and it doesn't hurt.
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
#include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
The highest supported frequency (1.2GHz) requires to "overvolt" the CPU.
However, some boards still do not have the cpu-supply DT property in the
cpu DT node which means that the CPU will always run with the same input
voltage but try to run at 1.2GHz frequency. This is the source of
(experienced) CPU crashes.
Remove the OPP which requires overvolting the CPU until all boards have
a cpu-supply property.
Fixes: 03749eb88e ("ARM: dts: sun8i: add opp-v2 table for A33")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The digital AIF interfaces has been renamed in the sun8i audio codec
driver so the audio-routing in the device tree must be renamed too.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that all resets added match the corresponding module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that all resets added match the corresponding module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The bl_en_pin GPIO pinmux is configured as "gpio_in", which makes it
conflicts with the real GPIO usage (out), and makes the backlight not
usable.
Drop the GPIO pinmux for it, thus this GPIO can be correctly used.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The CPU port of the BCM53125 is configured with RGMII (no delays) but
this should actually be RGMII with transmit delay (rgmii-txid) because
STMMAC takes care of inserting the transmitter delay. This fixes
occasional packet loss encountered.
Fixes: d7b9eaff5f ("ARM: dts: sun7i: Add BCM53125 switch nodes to the lamobo-r1 board")
Reported-by: Hartmut Knaack <knaack.h@gmx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds the Gemini power controller to the SoC DTSI
file.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adds crypto hardware (SPU) to Northstar Plus device tree file.
Signed-off-by: Steve Lin <steven.lin1@broadcom.com>
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Adds mailbox / PDC to NSP device tree. Needs new compatibility string
to differentiate from NS2 version.
Signed-off-by: Steve Lin <steven.lin1@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Adding ethernet aliases. These are used, for example, by bootloaders,
to modify the MAC addresses in the device tree.
Signed-off-by: Steve Lin <steven.lin1@broadcom.com>
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This is BCM47081A0 based home router with BCM43217 and BCM4352 wireless
chipsets.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The i2c device tree entry should be disabled by default to match the
current convention in other device tree files. Similarily, enable it on
the XMC board, where it is being used.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the EHCI and OHCI entries to the Northstar Plus device tree files.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add I2C support to the bcm5301x Device Tree. Since no driver changes
are needed to enable this hardware, only the device tree changes are
required to make this functional.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
GIC_PPI flags were misconfigured for the timers, resulting in errors
like:
[ 0.000000] GIC: PPI11 is secure or misconfigured
Changing them to being edge triggered corrects the issue
Suggested-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: d27509f1 ("ARM: BCM5301X: add dts files for BCM4708 SoC")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add OneNAND node for IGEP and leave it disabled by default. It is up
to bootloader to enable proper node. Timing just works, but values are
copied over from N900 as I was unable to find chip datasheet.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Note that early-bresp-disable and full-line-zero-disable are required
because the sideband signals between the CPU and L2C were not connected
in this SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
The libgpio code pre-sets the GPIO values for the gpio-reset in the
device tree. This results in the device being reset during bringup.
To prevent this pre-setting, use the "open-source" flag in the device
tree.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: b1aaf88 ("ARM: dts: NSP: Add GPIO reboot method to bcm958625hr DTS file")
Fixes: 10baed1 ("ARM: dts: NSP: Add GPIO reboot method to bcm958625xmc DTS file")
Fixes: 088e3148 ("ARM: dts: NSP: Add new DT file for bcm958522er")
Fixes: e3227c1 ("ARM: dts: NSP: Add new DT file for bcm958525er")
Fixes: 2f8bc00 ("ARM: dts: NSP: Add new DT file for bcm958622hr")
Fixes: d454c37 ("ARM: dts: NSP: Add new DT file for bcm958623hr")
Fixes: f27eacf ("ARM: dts: NSP: Add new DT file for bcm988312hr")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the dmas and dma-names properties to support HDMI audio.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Add the Altera Arria10 System Resource Reset Controller to the MFD
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2 change commit header to ARM: dts: socfpga.
dw-mmc got its reset-properties specified, so add the softresets
for it in rk3228/rk3229.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
dw-mmc got its reset-properties specified, so add the softresets
for it in rk3066/rk3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
dw-mmc got its reset-properties specified, so add the softresets
for it in rk3036.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
dw-mmc got its reset-properties specified, so add the softresets
for it in rk3288.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
The best place to register the CPU cooling device is from the cpufreq
driver as we would know if all the resources are already available or
not. That's what is done for the cpufreq-dt.c driver as well.
The cpu-cooling driver for dbx500 platform was just (un)registering
with the thermal framework and that can be handled easily by the cpufreq
driver as well and in proper sequence as well.
Get rid of the cooling driver and its its users and manage everything
from the cpufreq driver instead.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- Fix smartreflex platform data regression where I accidentally
removed legacy platform data still in use
- Fix hypervisor mode for thumb2 kernel
- Fix misplaced tpic2810 to move it to right bus
- Enable INPUT_MOUSEDEV as a loadable module have mice working
- Fix use of gpio-key,wakeup and use wakeup-source instead as
this accidentally sneaked in during the merge window
- Fix error handling for onenand to properly return error
- Remove legacy gpmc-nand.c that's now dead code, this
also removes dependency to the MTD tree for further driver
changes
- Fix device node reference count errors for omap3 and
related to it also release device nodes after no longer
needed
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Merge tag 'omap-for-v4.11/fixes-rc1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for v4.11-rc cycle:
- Fix smartreflex platform data regression where I accidentally
removed legacy platform data still in use
- Fix hypervisor mode for thumb2 kernel
- Fix misplaced tpic2810 to move it to right bus
- Enable INPUT_MOUSEDEV as a loadable module have mice working
- Fix use of gpio-key,wakeup and use wakeup-source instead as
this accidentally sneaked in during the merge window
- Fix error handling for onenand to properly return error
- Remove legacy gpmc-nand.c that's now dead code, this
also removes dependency to the MTD tree for further driver
changes
- Fix device node reference count errors for omap3 and
related to it also release device nodes after no longer
needed
* tag 'omap-for-v4.11/fixes-rc1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Release device node after it is no longer needed.
ARM: OMAP2+: Fix device node reference counts
ARM: OMAP2+: Remove legacy gpmc-nand.c
ARM: OMAP2+: gpmc-onenand: propagate error on initialization failure
ARM: dts: am335x-pcm953: Fix legacy wakeup source binding
ARM: omap2plus_defconfig: Enable INPUT_MOUSEDEV as loadable modules
ARM: dts: am57xx-idk: tpic2810 is on I2C bus, not SPI
ARM: OMAP5 / DRA7: Fix HYP mode boot for thumb2 build
ARM: OMAP3: Fix smartreflex platform data regression
Signed-off-by: Olof Johansson <olof@lixom.net>
please pull the following:
- Jon fixes the UART output on the Broadcom bcm953012k reference board by
using the proper clock reference instead of hard-coding the baud rate
- Jon also fixes the memory map on the bcm953012k reference board by using
the appropriate physical RAM start address
- Jon finally fixes the interrupt type for the Cortex A9 global and local
timers found in the BCM5301X SoC (Norsthar).
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Merge tag 'arm-soc/for-4.11/devicetree-fixes' of http://github.com/Broadcom/stblinux into fixes
This pull request contains Broadcom ARM-based SoC Device Tree fixes for 4.11,
please pull the following:
- Jon fixes the UART output on the Broadcom bcm953012k reference board by
using the proper clock reference instead of hard-coding the baud rate
- Jon also fixes the memory map on the bcm953012k reference board by using
the appropriate physical RAM start address
- Jon finally fixes the interrupt type for the Cortex A9 global and local
timers found in the BCM5301X SoC (Norsthar).
* tag 'arm-soc/for-4.11/devicetree-fixes' of http://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
ARM: dts: BCM5301X: Fix memory start address
ARM: dts: BCM5301X: Fix UARTs on bcm953012k
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the AB8500 clocks to the device tree using the new
bindings from the clk subsystem, making audio work again.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Watchdog module does not have external dependencies so it can be safely
enabled in exynos4.dtsi thus making it available for all Exynos4-based
boards.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Watchdog module does not have external dependencies so it can be safely
enabled in s3c64xx.dtsi thus making it available for all S3C64xx-based
boards.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250).
Just like the others, for working it requires additional steps in Power
Management Unit: unmasking the reset request and enabling the system
reset. Without these additional steps in PMU, the watchdog will not be
able to reset the system on expiration event.
Change the compatible of Exynos4412 watchdog device node to
samsung,exynos5250-wdt which includes the additional PMU steps.
This will also fix infinite watchdog interrupt in soft mode (lack of
interrupt clear) because it is also included in samsung,exynos5250-wdt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
The scif_clk device node is already enabled in r8a7794.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7794.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7793.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The pcie_bus_clk device node is already enabled in r8a7791.dtsi, so
there is no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk and pcie_bus_clk device nodes are already enabled in
r8a7791.dtsi, so there is no need to update their statuses again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7790.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7779.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The scif_clk device node is already enabled in r8a7778.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
While status "ok" does work, the canonical form is "okay", so update the
few places that used the former.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This devicetree is simply based on the board file in
arch/arm/mach-gemini/board-wbd222.c and contain the
equivalent platform data, mainly just moving the GPIOs
from the global numberspace to explicitly reference their
parent GPIO.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This devicetree is simply based on the board file in
arch/arm/mach-gemini/board-wbd111.c and contain the
equivalent platform data, mainly just moving the GPIOs
from the global numberspace to explicitly reference their
parent GPIO.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This devicetree is simply based on the board file in
arch/arm/mach-gemini/board-rut1xx.c and contain the
equivalent platform data, mainly just moving the GPIOs
from the global numberspace to explicitly reference their
parent GPIO.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This devicetree is simply based on the board file in
arch/arm/mach-gemini/board-nas4220b.c and contain the
equivalent platform data, mainly just moving the GPIOs
from the global numberspace to explicitly reference &gpio1.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a device tree for the Gemini SoC and the ITian
Square One SQ201 board that has been my testing target
for Gemini device tree support.
Cc: Janos Laube <janos.dev@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The eMMC devices on UniPhier boards are generally used in the 8-bit
mode. So, DAT4-7 pins should be controlled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These UniPhier DT files are fine as long as they are compiled in the
Linux build system. It is true that Linux is the biggest user of
DT, but DT is project neutral from its concept. DT files are often
re-used for other projects. Especially for the UniPhier platform,
these DT files are re-used for U-Boot as well.
If I feed these DT files to the FDTGREP tool in U-Boot, it complains
about the node order.
FDTGREP spl/u-boot-spl.dtb
Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
/aliases node must come before all other nodes
Given that DT is not very sensitive to the order of nodes, this is a
problem of FDTGREP. I filed a bug report a year ago, but it has not
been fixed yet.
Differentiating DT is painful. So, I am up-streaming the requirement
from the down-stream project.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on audio data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on audio data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock and the C4 power domain,
so it can be power managed using that clock in the future.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add watchdog timer support for RZ/A1.
For the RZ/A1, the only way to do a reset is to overflow the WDT, so this
is useful even if you don't need the watchdog functionality.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Such a trigger doesn't exist in Linux and is not needed as LED is being
turned off by default. This could cause errors in LEDs core code when
trying to set default trigger.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Such a trigger doesn't exist in Linux and is not needed as LED is being
turned off by default. This could cause errors in LEDs core code when
trying to set default trigger.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch updates the Duckbill device tree and synchronize it with
the vendor distributed file. The changes in mostly pin-muxing stuff,
but also some minor fixes. In detail:
- enable SPI pins
- enable I2C pins
- enable UART pins
- enable LRADC pin
- adjust USB DR mode
- add default triggers for LEDs
- get rid of regulators simple-bus container
- adjust phy reset duration
According to phy datasheet, 25ms are sufficient. This also reduces
the time to boot the system.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch renames mmc2_sck_cfg in order to prepare for an alternative
muxing setup.
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Quoting Philipp Zabel:
"Since this regulator is used as the TVDAC analog power supply, this
range should at least be limited to the analog power supply range of the
TVDAC, listed in Table 74-9. of the i.MX53 reference manual (2.5-2.75V).
But since the nominal voltage is 2.75V, which was used to determine the
analog gain that is supposed to result in the necessary 0.7V
peak-to-peak amplitude on the VGA output, I'd say we should just fix the
voltage to 2750000 here."
, so limit the TVDAC analog power supply as suggested.
Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The cm-fx6 module has an onboard Wolfson wm8731 codec which is muxed
to the ssi2 controller. Unlike most (all?) supported i.MX6 board/codec
combinations the wm8731 is operated in slave mode and the clock setup
is static.
Add support for it.
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
[christopher.spinrath@rwth-aachen.de: enhanced commit message, ported
to upstream and some cleanup]
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
After issuing a 'reboot' command the imx6sx-udoo-neo board does not
reboot as expected and it just hangs instead.
In mainline kernel only LDO enabled mode is supported. Do not provide
arm-supply/soc-supply nodes in the device tree, so that the board operates
in LDO enabled mode and can then successfully reboot via watchdog.
Fixes: 76e691fc76 ("ARM: dts: imx6sx: Add UDOO Neo support")
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port
0.1 MEM" range was errantly kept when creating a specific dts for the
SoC.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.
Moving the binding to the DFX block enables support for different clock
strapping options in hardware.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give some compatibility with the Marvell
supplied SDK.
As no upstream driver currently exists for this block and support for
this SoC is still quite fresh in the kernel it should not be necessary
to retain a backwards compatible binding.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
In others board we have the sata led set to function
with the sata led trigger by default.
This patch makes the same for these board that have sata
led but get disabled by not associating it to any trigger.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The mbus binding had been extended more than two years ago, but the
device tree files for Armada 38x didn't change.
Adding this third entry will allow the mbus going to suspend which was
the last thing preventing the SoC going to standby mode
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Linksys WRT1900ACS (Shelby) is another Armada 385 based router in
the Linksys WRT AC Series which got released in October 2015.
The file armada-385-linksys-shelby.dts is taken from OpenWrt as-is and
originally authored by Imre Kaloz.
URL: 8466384db1/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-shelby.dts
CC: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the burst and esc clock frequency properties to the parent (DSI node).
Currently the clock is parsed from the port node, while it should be
taken from the dsi node.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
In Odroid XU3 Lite board, the temperature levels reported for thermal
zone 0 were weird. In warm room:
/sys/class/thermal/thermal_zone0/temp:32000
/sys/class/thermal/thermal_zone1/temp:51000
/sys/class/thermal/thermal_zone2/temp:55000
/sys/class/thermal/thermal_zone3/temp:54000
/sys/class/thermal/thermal_zone4/temp:51000
Sometimes after booting the value was even equal to ambient temperature
which is highly unlikely to be a real temperature of sensor in SoC.
The thermal sensor's calibration (trimming) is based on fused values.
In case of the board above, the fused values are: 35, 52, 43, 58 and 43
(corresponding to each TMU device). However driver defined a minimum value
for fused data as 40 and for smaller values it was using a hard-coded 55
instead. This lead to mapping data from sensor to wrong temperatures
for thermal zone 0.
Various vendor 3.10 trees (Hardkernel's based on Samsung LSI, Artik 10)
do not impose any limits on fused values. Since we do not have any
knowledge about these limits, use 0 as a minimum accepted fused value.
This should essentially allow accepting any reasonable fused value thus
behaving like vendor driver.
The exynos5420-tmu-sensor-conf.dtsi is copied directly from existing
exynos4412 with one change - the samsung,tmu_min_efuse_value.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Add pcie-phy node to phy-exynos-pcie along with some changes to other
nodes:
1. Remove the configuration space from "ranges" property because this
was the old way of getting it. Preferred is to use "config" reg.
2. Use the reg-names as "elbi" and "config" so the purpose of addresses
will be easily known.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit adds the device tree description for the Synology DS116 NAS.
It is a one-bay NAS powered by a Marvell Armada 385 at 1.866 GHz. The
device features the following items :
- 1 GB DDR3 RAM
- a 8MB SPI flash
- 2 USB3 ports, power-controlled via a GPIO for each
- 1 gigabit ethernet interface connected over SGMII to a 88e1514 phy
- a single SATA port, power-controlled via a GPIO
- a battery-powered RTC
- one UART connected to the serial console (2mm connector on board)
- the Tx line of the second UART connected to a PIC microcontroller
dealing with beep, reset, power-off and LED blinking (9600 Bps)
- some of the front-panel LEDs are connected to GPIOs, one is directly
connected to the SATA link to report disk activity.
- a GPIO-controlled fan (3 bits for 7 speeds and OFF)
With this DTS, my NAS is 100% functional starting with kernel 4.9.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
As was done with Armada XP, add node labels to Armada 38x common and SoC
specific nodes to make them easier to reference in board device trees.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Leave pca953x P06,P07 pins on b850v3 platform and P06 pin on
b450v3/b650v3 unconfigured in the kernel space since they could be
configured as DP1_RST and DP2_RST by the applications for the DP FW
update support.
Signed-off-by: Ken Lin <ken.lin@advantech.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Extend the vpif node with an output port with a single channel.
NOTE: this is still mostly just hardware description - the actual
driver is registered using pdata-quirks. We need the node however
for correct pin control function selection.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We need the expander to be probed to allow the VPIF controller to
receive interrupts from the video decoder.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add a new pinctrl sub-node for vpif display pins. Move VP_CLKIN3 and
VP_CLKIN2 to the display node where they actually belong (vide section
36.2.2 of the OMAP-L138 technical reference manual).
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The da850-evm dts file contains whitespace errors in the vpif node.
This patch fixes them.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds a device tree node for sound on LEGO MINDSTORMS EV3. The EV3
uses one of the SoC PWMs connected to an amplifier to create sound from
a speaker.
The PWM is passed through a low-pass filter, so it is actually possible
to do PCM playback, but there is no existing driver, so just using
pwm-beeper for now, since it is also a compatible mode of operation.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds a node for the TI ADS7957 analog/digital converter on LEGO
MINDSTORMS EV3 as well as a regulator node that is used by the A/DC node.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.
Fixes: 34ea4b4a82 ("ARM: dts: r8a7794: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: ad53f5f00b ("ARM: dts: r8a7793: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 6f9314ce25 ("ARM: dts: r8a7791: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15/A7 cache controllers are integrated controllers, and thus
the device nodes representing them should not have unit-addresses or reg
properties.
Fixes: 2c3de36700 ("ARM: dts: r8a7790: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.
Fixes: c95360247b ("ARM: dts: r8a7745: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 34e8d993a6 ("ARM: dts: r8a7743: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15/A7 cache controllers are integrated controllers, and thus
the device nodes representing them should not have unit-addresses or reg
properties.
Fixes: b0da45c60d ("ARM: dts: r8a73a4: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
