Commit Graph

299347 Commits

Author SHA1 Message Date
Stephen Warren
c44e438a7f ARM: dt: tegra: gpio comment cleanup
Ensure that all Tegraa GPIO specifiers contain a comment indicating which
GPIO name the number refers to.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14 10:55:03 -06:00
Stephen Warren
f9eb26a4e1 ARM: dt: tegra: remove unnecessary unit addresses
DT node names only need to include the unit address if it's required to
make the node name unique. Remove the unnecessary unit addresses.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14 10:55:00 -06:00
Stephen Warren
95decf8474 ARM: dt: tegra: whitespace cleanup
Consistently don't place a space after < or before >.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14 10:54:55 -06:00
Stephen Warren
1dfebb426c ARM: dt: tegra cardhu: fix typo in SDHCI node name
Cardhu's eMMC controller is on sdhci@78000600, not sdhci@78000400.
Fix the typo. This roughly doubles the IO performance, since the
support-8bit property actually takes effect.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: stable@kernel.org # v3.4
2012-05-14 10:53:01 -06:00
Laxman Dewangan
331da58ca1 ARM: dt: tegra: cardhu: register core regulator tps62361
Add device info for the core regulator tps62360 in tegra-cardhu
dts file.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed node name to reflect actual device type]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:52:52 -06:00
hdoyu@nvidia.com
54174a33da ARM: dt: tegra30.dtsi: Add SMMU node
Add a node for the Tegra30 SMMU

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:52:00 -06:00
hdoyu@nvidia.com
6a943e0e13 ARM: dt: tegra20.dtsi: Add GART node
Add a node for the Tegra20 GART

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:51:55 -06:00
hdoyu@nvidia.com
ecf4374273 ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes
Add Tegra MC(Memory Controller) nodes for tegra30.dtsi.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:51:51 -06:00
hdoyu@nvidia.com
4a82f2b38e ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes
Add Tegra MC(Memory Controller) nodes for tegra20.dtsi.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:51:46 -06:00
Hiroshi DOYU
7868a9bcac ARM: dt: tegra: Add device tree support for AHB
Add AHB entry for tegra20/30.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14 10:51:28 -06:00
Stephen Warren
4b7e870590 Merge branch 'for-3.5/dt' into for-3.5/dt2-new 2012-05-14 10:48:24 -06:00
Stephen Warren
d9e33b593b Merge branch 'for-3.5/usb-ulpi' into for-3.5/dt2-new 2012-05-14 10:48:21 -06:00
Stephen Warren
22bfe102c0 ARM: dt: tegra trimslice: add support for audio
* Add node for the audio codec
* Enable Tegra's I2S1 controller and DAS
* Add node for top-level sound complex

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:14 -06:00
Stephen Warren
c7bd632e88 ARM: dt: tegra trimslice: enable SDHCI1 controller
This is the micro-SD card slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:13 -06:00
Stephen Warren
081cc0a57c ARM: dt: tegra trimslice: add RTC I2C device
According to the device's datasheet, it can support an interrupt too.
However, the existing board file doesn't specify an interrupt, and I
don't have the schematics, so I can't add an interrupts property. The
current Linux driver doesn't support anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:12 -06:00
Olof Johansson
45dbe9dd2c ARM: dt: tegra seaboard: add i2c devices
Add the known i2c devices on seaboard to the i2c table.

Also rename the temperature sensor device node, and mark it as a nct1008
instead of an adt7461 (which it is -- the chips are compatible though).

Signed-off-by: Olof Johansson <olof@lixom.net>
[swarren: Removed isl29018 from patch; it's already there now. Fixed
 interrupts properties now that Tegra GPIO is an interrupt controller.
 Moved smart-battery to the correct I2C bus.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:11 -06:00
Stephen Warren
802a849948 ARM: dt: tegra seaboard: configure I2C2 pinmux
The I2C2 controller can be routed to either pingroup DDC or PTA. Seaboard
actually uses this as an I2C bus mux, and devices are connected to both
pingroups. This change statically assigns the I2C2 controller to pingroup
PTA, so that on-board devices can be accessed. The DDC pingroup is used
for EDID/DDC accesses which are not yet required, given the absence of
any Tegra graphics support. I2C muxing will be supported later.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:10 -06:00
Stephen Warren
22bd1f7ef4 ARM: dt: tegra seaboard: fix I2C2 SCL rate
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:08 -06:00
Laxman Dewangan
b46b0b54de ARM: dt: tegra: enable als and proximity sensor
Add the device info for ALS and proximity sensor for tegra
boards cardhu, ventana and seaboard.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: s/PZ02/PZ2/ in .dts files, s/seabridge/seaboard/ in commit
 description]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-03 14:49:07 -06:00
Stephen Warren
563da21b1d ARM: dt: tegra: pinmux changes for USB ULPI
Ensure that the USB ULPI signals are not tri-stated, and have no pull-
up or pull-down.

Ensure that the pingroup hosting the USB ULPI reset signal (GPIO PV0 or
PV1 depending on the board, so UAC) is not tri-stated, and has no pull-
up or pull-down.

This change appears larger than it is due to the grouping and sorting of
the pin configuration data.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:10 -06:00
Stephen Warren
aa607ebf93 ARM: tegra: add USB ULPI PHY reset GPIO to device tree
ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:09 -06:00
Stephen Warren
60d148b9f8 ARM: tegra: don't hard-code USB ULPI PHY reset_gpio
Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of
hard-coding this GPIO into devices.c, make the board files set it
explicitly. This will allow the PHY code to differentiate between set and
unset values, and hence know when to read the value from device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:09 -06:00
Stephen Warren
9abafa021e ARM: tegra: change pll_p_out4's rate to 24MHz
pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:09 -06:00
Stephen Warren
7ff4db0967 ARM: tegra: fix pclk rate
Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the
rate of hclk. Since pclk is derived from that, and only has integer
dividers, the pclk rate needs to change in the same fashion, from 54MHz
to 60MHz.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:09 -06:00
Stephen Warren
60f975b98c ARM: tegra: reparent sclk to pll_c_out1
pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:09 -06:00
Allen Martin
c8b62ab41f ARM: tegra: Add pllc clock init table
pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
so that it's possible to explicitly initialize the PLL.

NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
whereas the ChromeOS kernel contains entries for 600MHz output. I chose
to upstream the ChromeOS values for now, since the 600MHz rate appears
to match the default rate of this PLL when the HW boots, and it's not
clear to me why 522 or 598MHz are more useful.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
[swarren: wrote commit description]
2012-04-25 15:22:09 -06:00
Stephen Warren
8c6a3852f6 ARM: dt: tegra cardhu: basic audio support
Add WM8903 codec nodes, and top-level sound complex node for basic
analog audio over headset jack and internal speakers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-25 15:22:01 -06:00
Stephen Warren
9ee6a5c4f4 ARM: dt: tegra30.dtsi: Add audio-related nodes
Add nodes for the Tegra30 AHUB and I2S controllers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-25 15:22:01 -06:00
Stephen Warren
5657d98dea ARM: tegra: add AUXDATA required for audio
Both the Tegra30 I2S and AHUB modules used clocks, and hence currently
require AUXDATA in order to get specific device names so that clock
lookups work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-25 15:22:01 -06:00
Stephen Warren
18b81fb733 ARM: tegra: set up audio clocks for tegra30 dt
Set up the audio clock tree for Tegra30 in an equivalent fashion to the
existing setup for Tegra20.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-25 15:22:01 -06:00
Peter De Schrijver
6437626928 ARM: tegra: Initialize pll_p_out1
pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be
initialized to make sure pll_a has a known input clock. Failure to do so
will cause the system to crash early in the bootup.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:22:01 -06:00
Stephen Warren
8703612b0a ARM: tegra: provide clock aliases for AHUB configlink
The Tegra30 AHUB driver must call tegra_periph_reset_deassert() for all
devices on the AHUB's configlink bus. The AHUB driver must be able to
call clk_get_sys() to retrieve the clock parameter for this function.
Add the necessary clock aliases to allow this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-25 15:22:01 -06:00
Stephen Warren
aef7704c6c pinctrl: tegra: error reporting cleanup
Print an explicit error message in various failure cases to allow
easier diagnosis.

WARN_ON() some internal failures that users/clients shouldn't be able to
trigger.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-04-25 15:21:47 -06:00
Stephen Warren
b5badbaad1 pinctrl: tegra: debugfs enhancements
* Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled.
* Implement pin_config_group_dbg_show op.
* Implement pin_config_config_dbg_show op.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 14:35:18 -06:00
Stephen Warren
52f48fe00f pinctrl: tegra: refactor probe handling
Rather than having a single tegra-pinctrl driver that determines whether
it's running on Tegra20 or Tegra30, instead have separate drivers for
each that call into utility functions to implement the majority of the
driver. This change is based on review feedback of the SPEAr pinctrl
driver, which had originally copied to Tegra driver structure.

This requires that the two drivers have unique names. Update a couple
spots in arch/arm/mach-tegra for the name change.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 10:26:40 -06:00
Stephen Warren
ecc295bbab ARM: dt: tegra20: add pinmux to device tree
This adds a complete pinmux configuration to all Tegra20 device tree
files. This allows removal of board-dt-tegra20.c's use of the pinmux
board files, and the special device tree handling in board-pinmux.c.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:39 -06:00
Stephen Warren
e5cbeef0a4 ARM: dt: tegra cardhu: add pinmux to device tree
This adds a minimal pinmux configuration to the Tegra Cardhu device
tree. Initially, just the built-in eMMC and SD card slot are configured.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net
2012-04-18 10:26:39 -06:00
Stephen Warren
b7449d95b0 ARM: tegra: Remove pre-pinctrl pinmux driver
The pinctrl driver is now active and used by all boards. Remove the
old pinmux driver.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:39 -06:00
Stephen Warren
f30d12b3ff ARM: tegra: Switch to new pinctrl driver
* Rename old pinmux and new pinctrl platform driver and DT match table
  entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
  pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
  in pinctrl format.

Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.

All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.

Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.

Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:39 -06:00
Stephen Warren
3e215d0a19 gpio: tegra: Hide tegra_gpio_enable/disable()
Recent pinctrl discussions concluded that gpiolib APIs should in fact do
whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
required. This change implements this for the Tegra GPIO driver, and removes
calls to the Tegra-specific APIs from drivers and board files.

Cc: Chris Ball <cjb@laptop.org>
Cc: linux-mmc@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Chris Ball <cjb@laptop.org> # for sdhci-tegra.c
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:38 -06:00
Stephen Warren
c61b3da0ac ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQ
Don't call gpio_request() or gpio_direction_input() for ISL29018_IRQ.
This pin is only used as an IRQ, and hence no GPIO configuration should
be necessary; the GPIO/IRQ driver should (and does) perform any required
setup when the IRQ is requested.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:38 -06:00
Stephen Warren
d941136fc6 gpio: tegra: configure pins during irq_set_type
When a Tegra GPIO is used as an IRQ, it should be enabled as a GPIO (so
the pinmux module isn't driving it as an output) and configured as a GPIO
input (so the GPIO module isn't driving it as an output). Set this up
automatically whenever an IRQ is requested, so that users of IRQs don't
need to do this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:38 -06:00
Stephen Warren
4bee6417c9 ARM: tegra: Remove VBUS_GPIO handling from board files
Instead of having board files manually request and initialize USB VBUS
GPIOs, fill in the USB driver's platform data and have it do it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:37 -06:00
Stephen Warren
434103adea usb: ehci-tegra: Add vbus_gpio to platform data
Add a vbus_gpio field to platform data. This mirrors the device tree
property nvidia,vbus-gpio. This makes the VBUS GPIO handling identical
between booting with board files and device tree; the driver always does
it.

This removes the need for board files to request and initialize the GPIO
early during their boot process, perhaps even before the GPIO driver is
ready to process the request.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
2012-04-18 10:26:37 -06:00
Dong Aisheng
dcb5dbc305 pinctrl: show pin name for pingroups in sysfs
Pin name is more useful to users.

After change, when cat pingroups in sysfs, it becomes:
root@freescale /sys/kernel/debug/pinctrl/20e0000.iomuxc$ cat pingroups
registered pin groups:
group: uart4grp-1
pin 219 (MX6Q_PAD_KEY_ROW0)
pin 218 (MX6Q_PAD_KEY_COL0)

group: usdhc4grp-1
pin 305 (MX6Q_PAD_SD4_CMD)
pin 306 (MX6Q_PAD_SD4_CLK)
pin 315 (MX6Q_PAD_SD4_DAT0)
pin 316 (MX6Q_PAD_SD4_DAT1)
pin 317 (MX6Q_PAD_SD4_DAT2)
pin 318 (MX6Q_PAD_SD4_DAT3)
pin 319 (MX6Q_PAD_SD4_DAT4)
pin 320 (MX6Q_PAD_SD4_DAT5)
pin 321 (MX6Q_PAD_SD4_DAT6)
pin 322 (MX6Q_PAD_SD4_DAT7)

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:13 +02:00
Dong Aisheng
d0bd8df56e pinctrl: show pin name when request pins
Pin name is more useful to users.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:13 +02:00
Stephen Warren
6d4ca1fb46 pinctrl: implement devm_pinctrl_get()/put()
These functions allow the driver core to automatically clean up any
allocations made by drivers, thus leading to simplified drivers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:13 +02:00
Dong Aisheng
2aeefe0233 pinctrl: a minor fix of pin config debug information
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:13 +02:00
Viresh Kumar
96593afe6d pinctrl: pinconf: fix compilation error if PINCONF is not selected
When we compile pinctrl layer for platforms without CONFIG_PINCONF, we get
following compilation errors:

drivers/built-in.o: In function `pinctrl_show':
linux-2.6/drivers/pinctrl/core.c:1116: undefined
reference to `pinconf_show_setting'
drivers/built-in.o: In function `pinctrl_maps_show':
linux-2.6/drivers/pinctrl/core.c:1071: undefined
reference to `pinconf_show_map'
drivers/built-in.o: In function `pinctrl_init_device_debugfs':
linux-2.6/drivers/pinctrl/core.c:1224: undefined
reference to `pinconf_init_device_debugfs'
make[1]: *** [.tmp_vmlinux1] Error 1

This patch fixes this.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:12 +02:00
Stephen Warren
6cb4158757 pinctrl: allow pctldevs to decode pin config in debugfs
Add a pinconf op so that pin controller drivers can decode their pin
config settings for debugfs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:12 +02:00