Commit Graph

482210 Commits

Author SHA1 Message Date
John Crispin
b96e6e9fd2 MIPS: ralink: allow loading irq registers from the devicetree
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8029/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:25 +01:00
John Crispin
53263a1c68 MIPS: ralink: add mt7628an support
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8031/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:24 +01:00
John Crispin
1dc5c2cfc1 MIPS: ralink: add support for MT7620n
This is the small version of MT7620a.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8030/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:24 +01:00
John Crispin
a097b13c52 MIPS: ralink: cleanup early_printk
Add support for the new MT7621/8 SoC and kill ifdefs.
Cleanup some whitespace error while we are at it.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8028/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:24 +01:00
John Crispin
f576fb6a07 MIPS: ralink: cleanup the soc specific pinmux data
Before we had a pinctrl driver we used a custom OF api. This patch converts the
soc specific pinmux data to a new set of structs. We also add some new pinmux
setings.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8009/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:24 +01:00
John Crispin
4248f7f121 MIPS: ralink: copy the commandline from the devicetree
This is a regression caused by:
commit afb46f7996
Author: Rob Herring <robh@kernel.org>
Date:   Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree

Make the of init code reuse the cmdline defined inside the dts.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8008/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:23 +01:00
John Crispin
7a1a44c909 MIPS: ralink: add a bootrom dumper module
This patch adds a trivial driver that allows userland to extract the bootrom of
a SoC via debugfs.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8002/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:22 +01:00
John Crispin
1e209c969a MIPS: ralink: add rt3883 wmac clock
Register the wireless mac clock on rti3883. This is required by the wifi driver.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8007/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:20 +01:00
John Crispin
f2a8bd2e92 MIPS: ralink: add rt2880 wmac clock
Register the wireleass mac clock on rt2880. This is required by the wifi driver.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8006/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:20 +01:00
John Crispin
a8b6204761 MIPS: ralink: add missing clk_set_rate() to clk.c
This function was missing causing make allmod to fail.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8005/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:20 +01:00
John Crispin
15d1112070 MIPS: ralink: allow manual memory override
RT5350 relies on the bootloader setting up the memc correctly. On some boards
the setup is incorrect leading to 32 MB being available but only 16 MB being
recognized. Allow these boards to manually override the memory range.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8004/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:20 +01:00
John Crispin
5433acd81e MIPS: ralink: add illegal access driver
These SoCs have a special irq that fires upon an illegal memmory access.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:19 +01:00
John Crispin
47e14d6678 MIPS: ralink: add rt_sysc_m32 helper
We already have a read and write wrapper. This adds the missing mask wrapper.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8001/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:19 +01:00
John Crispin
2920b83d35 MIPS: ralink: add a helper for reading the ECO version
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8000/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:19 +01:00
John Crispin
2adf550f26 MIPS: ralink: add verbose pmu info
Print the PMU and LDO settings on boot.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/7999/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:19 +01:00
John Crispin
9bc7ebcbf1 MIPS: lantiq: add missing spi clock on falcon SoC
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8050/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:18 +01:00
John Crispin
eb5dbd22b6 MIPS: lantiq: the detection of the gpe clock is broken
The code to detect unfused SoCs was broken due to missing register masking.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8049/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:18 +01:00
John Crispin
17327862f3 MIPS: lantiq: copy the commandline from the devicetree
This is a regression caused by:
commit afb46f7996
Author: Rob Herring <robh@kernel.org>
Date:   Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree

Make the of init code reuse the cmdline defined inside the dts.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8048/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:18 +01:00
John Crispin
d32caf94e0 MIPS: lantiq: move eiu init after irq_domain register
The eiu init failed as the irq_domain was not yet available.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8047/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:18 +01:00
John Crispin
e8b8ca8cb3 MIPS: lantiq: export soc type
The voice and dsl drivers need to know which SoC we are running on.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/8046/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:18 +01:00
John Crispin
276229d2a9 MIPS: lantiq: add support for xrx200 firmware depending on soc type
VR9 needs different firmware files for the various phy/soc revisions. Some
boards are ship with older and newer SoC revisions. To be able to boot a single
image on all versions we need to define both firmware files inside the
devicetree.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8045/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:17 +01:00
John Crispin
50128fe816 MIPS: lantiq: reboot gphy on restart
A reboot sometimes lead to a none working phy. An explicit reboot fixes the
problem.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8044/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:17 +01:00
John Crispin
c530781c93 MIPS: lantiq: add reset-controller api support
Add a reset-controller binding for the reset registers found on the lantiq
SoC.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8043/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:17 +01:00
John Crispin
05637f10e7 MIPS: lantiq: handle vmmc memory reservation
The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)"
which is used to run the voice firmware. This driver allows us to register
a chunk of memory that the voice driver can later use for the 2nd core.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8042/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:17 +01:00
Tomeu Vizoso
24c71c83ed MIPS: Alchemy: Remove direct access to prepare_count field of struct clk
Replacing it with a call to __clk_is_prepared(), which isn't entirely
equivalent but in practice shouldn't matter.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8120/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:17 +01:00
Andrew Bresticker
a45da56598 clocksource: mips-gic: Bump up rating of GIC timer
Bump up the rating of the GIC timer so that it gets prioritized
over the CP0 timer.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:16 +01:00
Andrew Bresticker
b695d8e6ad clocksource: mips-gic: Use clockevents_config_and_register
Use clockevents_config_and_register to setup the clock_event_device
based on frequency and min/max ticks instead of doing it ourselves.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:16 +01:00
Andrew Bresticker
e4752dbbc3 clocksource: mips-gic: Use CPU notifiers to setup the timer
Instead of requiring an explicit call to gic_clockevent_init in the SMP
startup path, use CPU notifiers to register and enable the GIC timer on
CPU startup.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8139/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:16 +01:00
Andrew Bresticker
f7ea3060b6 clocksource: mips-gic: Use percpu_dev_id
Since the GIC timer IRQ is a percpu IRQ, we can use percpu_dev_id
to pass the IRQ handler the correct clock_event_device.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8138/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:15 +01:00
Andrew Bresticker
001f5fe72c clocksource: mips-gic: Remove gic_event_handler
Remove gic_event_handler since it is completely unnecessary.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:15 +01:00
Andrew Bresticker
b085451453 clocksource: mips-gic: Move gic_frequency to clocksource driver
There's no reason for gic_frequency to be global any more and it
certainly doesn't belong in the GIC irqchip driver, so move it to
the GIC clocksource driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8137/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:15 +01:00
Andrew Bresticker
5fee56e0dd clocksource: mips-gic: Staticize local symbols
There are a number of variables and functions which are unnecessarily
global.  Mark them static.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:15 +01:00
Andrew Bresticker
a331ce63c8 clocksource: mips-gic: Combine with GIC clockevent driver
Combine the GIC clocksource driver with the GIC clockevent driver from
arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate
Kconfig symbol.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8132/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:15 +01:00
Andrew Bresticker
fa5635a277 MIPS: Move GIC clocksource driver to drivers/clocksource/
Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8133/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:14 +01:00
Andrew Bresticker
53a7bc815a irqchip: mips-gic: Use GIC_SH_WEDGE_{SET,CLR} macros
Use the GIC_SH_WEDGE_{SET,CLR} macros provided by mips-gic.h.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8134/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:14 +01:00
Andrew Bresticker
8f5ee79c92 irqchip: mips-gic: Remove gic_{pending,itrmask}_regs
There's no reason for the pending and masked interrupt bitmasks
to be global.  Just declare them on the stack in gic_get_int()
since they only consume (256*2)/8 = 64 bytes.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8131/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:14 +01:00
Andrew Bresticker
fb8f7be129 irqchip: mips-gic: Clean up #includes
Sort the #includes and remove those which are unnecessary.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8130/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:14 +01:00
Andrew Bresticker
824f3f7fa2 irqchip: mips-gic: Clean up header file
Remove duplicate #defines and unnecessary #includes, fix parenthesization,
and re-order register definitions in ascending order.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8128/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:13 +01:00
Kevin Cernekee
7110e227c8 MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driver
This hardware shows up on the newly-supported BCM3384 cable chip, as well
as several old BCM63xx DSL chips.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8172/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:13 +01:00
Kevin Cernekee
a2f6734c5f MAINTAINERS: Add entry for BCM33xx cable chips
Add myself as a maintainer for the new BCM3384 board support code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8171/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:13 +01:00
Kevin Cernekee
d666cd0246 MIPS: bcm3384: Initial commit of bcm3384 platform support
This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000)
application processor, with fully functional UART and USB 1.1/2.0.
Device Tree is used to configure the following items:

 - All peripherals
 - Early console base address
 - SMP or UP mode
 - MIPS counter frequency
 - Memory size / regions
 - DMA offset
 - Kernel command line

The DT-enabled bootloader and build instructions are posted at
https://github.com/Broadcom/aeolus

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8170/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:13 +01:00
Kevin Cernekee
ab81ce6217 Documentation: DT: Add "mti" vendor prefix
We have a bunch of platforms using "mti,cpu-interrupt-controller" but
the "mti" prefix isn't documented.  Fix this.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8169/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:12 +01:00
Kevin Cernekee
846deacebf Documentation: DT: Add entries for BCM3384 and its peripherals
This covers the new "brcm,*" devices added in the upcoming bcm3384 commit.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8168/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:12 +01:00
Kevin Cernekee
84988c0681 MIPS: Create a helper function for DT setup
A couple of platforms register two buses and call of_platform_populate().
Move this into a common function to reduce duplication.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8167/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:12 +01:00
Kevin Cernekee
68e6a78373 MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)
This is a dual core (quad thread) BMIPS5000.  It needs a little extra
code to boot the second core (CPU2/CPU3), but for now we can treat it the
same as a single core BMIPS5000.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8166/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:12 +01:00
Kevin Cernekee
d74b0172e4 MIPS: BMIPS: Add special cache handling in c-r4k.c
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.

BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$.  But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:12 +01:00
Kevin Cernekee
d8010ceba6 MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1
input, generating spurious IRQs.  In this case we want the platform code
to be able to mask it off.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8163/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:11 +01:00
Kevin Cernekee
bbf2ba67cd MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size.  If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:11 +01:00
Kevin Cernekee
a7ef1eaddb MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes
CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c.  However,
it is currently hardwired to use an L1_SHIFT of 6 (64 bytes).  Move the
L1_SHIFT selection into the CPU or SoC section so that other SoCs can
select different values.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8162/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:11 +01:00
Kevin Cernekee
3677a28362 MIPS: BMIPS: Explicitly configure reset vectors prior to secondary boot
The secondary CPU's reset vector needs to be set to KSEG1 for a cold
boot (release from reset), or KSEG0 for a warm restart.  On a cold boot
KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may
be unavailable (XKS01 mode on 4380 or 5000).

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8161/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:10 +01:00