Commit Graph

83145 Commits

Author SHA1 Message Date
Shawn Guo
009e63f8d1 ARM: imx: compile fix for hotplug.c
Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing
from platforms) removes include of <asm/cacheflush.h> and hence
discovers a few indirect inclusion and declaration problems as below.

  CC      arch/arm/mach-imx/hotplug.o
In file included from arch/arm/mach-imx/hotplug.c:16:0:
arch/arm/mach-imx/common.h💯29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default]
arch/arm/mach-imx/common.h💯29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
arch/arm/mach-imx/common.h:101:29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default]
arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_die’:
arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ‘cpu_do_idle’ [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_kill’:
arch/arm/mach-imx/hotplug.c:58:26: error: ‘jiffies’ undeclared (first use in this function)
arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ‘msecs_to_jiffies’ [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ‘time_after’ [-Werror=implicit-function-declaration]

Fix them by adding the needed inclusion and declaration.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-05-09 13:05:22 -07:00
Olof Johansson
5497e7b896 Merge branch 'late/fixes' into fixes
* late/fixes:
  ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP
  ARM: ux500: always select ABX500_CORE
  ARM: SIRF: select SMP_ON_UP only on SMP builds
  ARM: SPEAr: conditionalize l2x0 support
  ARM: imx: build CPU suspend code only when needed
  ARM: OMAP: build SMP code only for OMAP4/5
  ARM: tegra: Tegra114 needs CPU_FREQ_TABLE
  ARM: default machine descriptor for multiplatform

Signed-off-by: Olof Johansson <olof@lixom.net>
2013-05-09 13:05:15 -07:00
Al Viro
c5ddd2024a switch compat_sys_sysctl to COMPAT_SYSCALL_DEFINE
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-05-09 14:53:20 -04:00
Al Viro
6dd9148bc5 unicore32: just use mmap_pgoff()...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-05-09 14:10:07 -04:00
Denis Efremov
4833d7f0a8 arch/tile: remove inline marking of EXPORT_SYMBOL functions
EXPORT_SYMBOL and inline directives are contradictory to each other.
The patch fixes this inconsistency.

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Denis Efremov <yefremov.denis@gmail.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-05-09 13:53:45 -04:00
Al Viro
91c2e0bcae unify compat fanotify_mark(2), switch to COMPAT_SYSCALL_DEFINE
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-05-09 13:46:38 -04:00
Linus Torvalds
e15e611906 PCI updates for v3.10:
MSI
       PCI: Set ->mask_pos correctly
   Hotplug
       PCI: Delay final fixups until resources are assigned
   Moorestown
       x86/pci/mrst: Use configuration mechanism 1 for 00:00.0, 00:02.0, 00:03.0
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Merge tag 'pci-v3.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "MSI:
      PCI: Set ->mask_pos correctly
  Hotplug:
      PCI: Delay final fixups until resources are assigned
  Moorestown:
      x86/pci/mrst: Use configuration mechanism 1 for 00:00.0, 00:02.0, 00:03.0"

* tag 'pci-v3.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: Delay final fixups until resources are assigned
  x86/pci/mrst: Use configuration mechanism 1 for 00:00.0, 00:02.0, 00:03.0
  PCI: Set ->mask_pos correctly
2013-05-09 10:21:44 -07:00
Geert Uytterhoeven
0757f6159f xtensa simdisk: Fix proc_create_data() conversion fallout
arch/xtensa/platforms/iss/simdisk.c: In function 'proc_read_simdisk':
arch/xtensa/platforms/iss/simdisk.c:220:12: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]
arch/xtensa/platforms/iss/simdisk.c: In function 'proc_write_simdisk':
arch/xtensa/platforms/iss/simdisk.c:241:38: error: 'buffer' undeclared (first use in this function)
arch/xtensa/platforms/iss/simdisk.c:241:38: note: each undeclared identifier is reported only once for each function it appears in

Introduced by commit a69755b187 ("xtensa
simdisk: switch to proc_create_data()")

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-05-09 13:20:20 -04:00
Linus Torvalds
a637b0d459 - Lots of cleanups from Artem, including deletion of some obsolete drivers
- Support partitions larger than 4GiB in device tree
 - Support for new SPI chips
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Merge tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd

Pull MTD update from David Woodhouse:

 - Lots of cleanups from Artem, including deletion of some obsolete
   drivers

 - Support partitions larger than 4GiB in device tree

 - Support for new SPI chips

* tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd: (83 commits)
  mtd: omap2: Use module_platform_driver()
  mtd: bf5xx_nand: Use module_platform_driver()
  mtd: denali_dt: Remove redundant use of of_match_ptr
  mtd: denali_dt: Change return value to fix smatch warning
  mtd: denali_dt: Use module_platform_driver()
  mtd: denali_dt: Fix incorrect error check
  mtd: nand: subpage write support for hardware based ECC schemes
  mtd: omap2: use msecs_to_jiffies()
  mtd: nand_ids: use size macros
  mtd: nand_ids: improve LEGACY_ID_NAND macro a bit
  mtd: add 4 Toshiba nand chips for the full-id case
  mtd: add the support to parse out the full-id nand type
  mtd: add new fields to nand_flash_dev{}
  mtd: sh_flctl: Use of_match_ptr() macro
  mtd: gpio: Use of_match_ptr() macro
  mtd: gpio: Use devm_kzalloc()
  mtd: davinci_nand: Use of_match_ptr()
  mtd: dataflash: Use of_match_ptr() macro
  mtd: remove h720x flash support
  mtd: onenand: remove OneNAND simulator
  ...
2013-05-09 10:15:46 -07:00
Linus Torvalds
5647ac0ad4 Removal of GENERIC_GPIO for v3.10
GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any valid
 cases for enableing GENERIC_GPIO without GPIOLIB, even though it is
 possible to do so which has been causing confusion and breakage. This
 branch does the work to completely eliminate GENERIC_GPIO.
 
 However, it is not trivial to just create a branch to remove it. Over
 the course of the v3.9 cycle more code referencing GENERIC_GPIO has been
 added to linux-next that conflicts with this branch. The following must
 be done to resolve the conflicts when merging this branch into mainline:
 
 * "git grep CONFIG_GENERIC_GPIO" should return 0 hits. Matches should be
   replaced with CONFIG_GPIOLIB
 * "git grep '\bGENERIC_GPIO\b'" should return 1 hit in the Chinese
   documentation.
 * Selectors of GENERIC_GPIO should be turned into selectors of GPIOLIB
 * definitions of the option in architecture Kconfig code should be deleted.
 
 Stephen has 3 merge fixup patches[1] that do the above. They are currently
 applicable on mainline as of May 2nd.
 
 [1] http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg428056.html
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Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux

Pull removal of GENERIC_GPIO from Grant Likely:
 "GENERIC_GPIO now synonymous with GPIOLIB.  There are no longer any
  valid cases for enableing GENERIC_GPIO without GPIOLIB, even though it
  is possible to do so which has been causing confusion and breakage.
  This branch does the work to completely eliminate GENERIC_GPIO."

* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux:
  gpio: update gpio Chinese documentation
  Remove GENERIC_GPIO config option
  Convert selectors of GENERIC_GPIO to GPIOLIB
  blackfin: force use of gpiolib
  m68k: coldfire: use gpiolib
  mips: pnx833x: remove requirement for GENERIC_GPIO
  openrisc: default GENERIC_GPIO to false
  avr32: default GENERIC_GPIO to false
  xtensa: remove explicit selection of GENERIC_GPIO
  sh: replace CONFIG_GENERIC_GPIO by CONFIG_GPIOLIB
  powerpc: remove redundant GENERIC_GPIO selection
  unicore32: default GENERIC_GPIO to false
  unicore32: remove unneeded select GENERIC_GPIO
  arm: plat-orion: use GPIO driver on CONFIG_GPIOLIB
  arm: remove redundant GENERIC_GPIO selection
  mips: alchemy: require gpiolib
  mips: txx9: change GENERIC_GPIO to GPIOLIB
  mips: loongson: use GPIO driver on CONFIG_GPIOLIB
  mips: remove redundant GENERIC_GPIO select
2013-05-09 09:59:16 -07:00
Linus Torvalds
1763e735b0 Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine updates from Vinod Koul:
 "This time we have dmatest improvements from Andy along with dw_dmac
  fixes.  He has also done support for acpi for dmanegine.

  Also we have bunch of fixes going in DT support for dmanegine for
  various folks.  Then Haswell and other ioat changes from Dave and
  SUDMAC support from Shimoda."

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (53 commits)
  dma: tegra: implement suspend/resume callbacks
  dma:of: Use a mutex to protect the of_dma_list
  dma: of: Fix of_node reference leak
  dmaengine: sirf: move driver init from module_init to subsys_initcall
  sudmac: add support for SUDMAC
  dma: sh: add Kconfig
  at_hdmac: move to generic DMA binding
  ioatdma: ioat3_alloc_sed can be static
  ioatdma: Adding write back descriptor error status support for ioatdma 3.3
  ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap
  ioatdma: Adding support for 16 src PQ ops and super extended descriptors
  ioatdma: Removing hw bug workaround for CB3.x .2 and earlier
  dw_dmac: add ACPI support
  dmaengine: call acpi_dma_request_slave_channel as well
  dma: acpi-dma: introduce ACPI DMA helpers
  dma: of: Remove unnecessary list_empty check
  DMA: OF: Check properties value before running be32_to_cpup() on it
  DMA: of: Constant names
  ioatdma: skip silicon bug workaround for pq_align for cb3.3
  ioatdma: Removing PQ val disable for cb3.3
  ...
2013-05-09 09:46:45 -07:00
Vineet Gupta
5bba49f539 ARC: [mm] Aliasing VIPT dcache support 4/4
Enforce congruency of userspace shared mappings

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 22:00:57 +05:30
Vineet Gupta
de2a852cc0 ARC: [mm] Aliasing VIPT dcache support 3/4
Fix the one zillion warnings

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 22:00:57 +05:30
Vineet Gupta
4102b53392 ARC: [mm] Aliasing VIPT dcache support 2/4
This is the meat of the series which prevents any dcache alias creation
by always keeping the U and K mapping of a page congruent.
If a mapping already exists, and other tries to access the page, prev
one is flushed to physical page (wback+inv)

Essentially flush_dcache_page()/copy_user_highpage() create K-mapping
of a page, but try to defer flushing, unless U-mapping exist.
When page is actually mapped to userspace, update_mmu_cache() flushes
the K-mapping (in certain cases this can be optimised out)

Additonally flush_cache_mm(), flush_cache_range(), flush_cache_page()
handle the puring of stale userspace mappings on exit/munmap...

flush_anon_page() handles the existing U-mapping for anon page before
kernel reads it via the GUP path.

Note that while not complete, this is enough to boot a simple
dynamically linked Busybox based rootfs

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 21:59:46 +05:30
Vineet Gupta
6ec18a81b2 ARC: [mm] Aliasing VIPT dcache support 1/4
This preps the low level dcache flush helpers to take vaddr argument in
addition to the existing paddr to properly flush the VIPT dcache

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 21:53:16 +05:30
Jason Cooper
914dc329ee ARM: dts: don't assume boards are using twl4030 for omap3
If a board isn't using twl4030, then dtc will complain about the missing
phandle (which is in twl4030.dtsi).  Move the phy declaration to the dts
files.

Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-09 09:06:57 -07:00
Tony Lindgren
b1dd11d60e ARM: OMAP2+: Remove bogus IS_ERR_OR_NULL checking from id.c
Commit 6770b211 (ARM: OMAP2+: Export SoC information to userspace)
had some broken return value handling as noted by Russell King:

+       soc_dev = soc_device_register(soc_dev_attr);
+       if (IS_ERR_OR_NULL(soc_dev)) {
+               kfree(soc_dev_attr);
+               return;
+       }
+
+       parent = soc_device_to_device(soc_dev);
+       if (!IS_ERR_OR_NULL(parent))
+               device_create_file(parent, &omap_soc_attr);

This is nonsense.  For the first, IS_ERR() is sufficient.  For the second,
tell me what error checking is required in the return value of this
function:

struct device *soc_device_to_device(struct soc_device *soc_dev)
{
        return &soc_dev->dev;
}

when you've already determined that the passed soc_dev is a valid pointer.
If you read the comments against the prototype:

/**
 * soc_device_to_device - helper function to fetch struct device
 * @soc: Previously registered SoC device container
 */
struct device *soc_device_to_device(struct soc_device *soc);

if "soc" is valid, it means the "previously registered SoC device container"
must have succeeded and that can only happen if the struct device has been
registered.  Ergo, there will always be a valid struct device pointer for
any registered SoC device container.  Therefore, if soc_device_register()
succeeds, then the return value from soc_device_to_device() will always be
valid and no error checking of it is required.

Simples.  The rule as ever applies here: get to know the APIs your using
and don't fumble around in the dark hoping that you'll get this stuff
right.

Fix it as noted by Russell.

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-09 09:06:27 -07:00
Ralf Baechle
b22d1b6a91 Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next 2013-05-09 17:57:30 +02:00
Ralf Baechle
5e0e61dd2c Merge branch 'next/kvm' into mips-for-linux-next 2013-05-09 17:56:40 +02:00
Raghu Gandham
0ab2b7d08e MIPS: Add new GIC clockevent driver.
Add new clockevent driver that uses the counter present on the MIPS
Global Interrupt Controller.

Signed-off-by: Raghu Gandham <Raghu.Gandham@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:21 +02:00
Steven J. Hill
2675fa7c7b MIPS: Formatting clean-ups for clocksources.
Various whitespace and #ifdef removals for GIC and R4K clocksources.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:21 +02:00
Steven J. Hill
dfa762e1c3 MIPS: Refactor GIC clocksource code.
Reorganize some of the GIC clocksource driver code. Below is a list of
the various changes.

  * No longer select CSRC_GIC by default for Malta platform.
  * Limit choice for either the GIC or R4K clocksource, not both.
  * Change location in Makefile.
  * Created new 'gic_read_count' function in common 'irq-gic.c' file.
  * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function.
  * Surround GIC specific code in Malta platform code with #ifdef's.
  * Only initialize the GIC clocksource if it was selected. Original
    code called it unconditionally if a GIC was found.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
28ea215186 MIPS: Move 'gic_frequency' to common location.
Move the global variable 'gic_frequency' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
ff86714fda MIPS: Move 'gic_present' to common location.
Move the global variable 'gic_present' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
451b001b05 MIPS: MIPS16e: Add unaligned access support.
Add logic needed to handle unaligned accesses in MIPS16e mode.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
8508488fe7 MIPS: MIPS16e: Support handling of delay slots.
Add logic needed to properly calculate exceptions for delay slots
when in MIPS16e mode.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
cd574704ec MIPS: MIPS16e: Add instruction formats.
Add structures for all the MIPS16e instructions. Also add the
enumerations for all the bit fields for opcodes, functions, etc.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
3e9f37e885 MIPS: microMIPS: Optimise 'strnlen' core library function.
Optimise 'strnlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:20 +02:00
Steven J. Hill
b1bac37345 MIPS: microMIPS: Optimise 'strlen' core library function.
Optimise 'strlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill
0131f2b2c9 MIPS: microMIPS: Optimise 'strncpy' core library function.
Optimise 'strncpy' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill
26c5e07d14 MIPS: microMIPS: Optimise 'memset' core library function.
Optimise 'memset' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill
bce860833a MIPS: microMIPS: Add configuration option for microMIPS kernel.
This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill
1658f914ff MIPS: microMIPS: Disable LL/SC and fix linker bug.
Partially revert commit e0c14a260d66ba35935600d6435940a566fe806b
and turn off LL/SC when building a pure microMIPS kernel. This is
a temporary fix until the cmpxchg assembly macro functions are
re-written to not use the HI/LO registers in address calculations.

Also add .insn in selected user access functions which would
otherwise produce ISA mode jump incompatibilities. This is also a
temporary fix.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Douglas Leung
01be057b33 MIPS: microMIPS: Add vdso support.
Support vdso in microMIPS mode.

Signed-off-by: Douglas Leung <Douglas.Leung@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Leonid Yegoshin
34c2f668d0 MIPS: microMIPS: Add unaligned access support.
Add logic needed to handle unaligned accesses in microMIPS mode.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
2013-05-09 17:55:19 +02:00
Leonid Yegoshin
fb6883e580 MIPS: microMIPS: Support handling of delay slots.
Add logic needed to properly calculate exceptions for delay slots
when in microMIPS mode.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill
2a0b24f56c MIPS: microMIPS: Add support for exception handling.
All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Leonid Yegoshin
102cedc32a MIPS: microMIPS: Floating point support.
Add logic needed to do floating point emulation in microMIPS mode.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill
cf6d905828 MIPS: microMIPS: Fix macro naming in micro-assembler.
The macros did not properly take into account the ISA that
the kernel was being compiled with. A classic MIPS kernel
will have the standard 'uasm_i_##op' macro functions with
'MM_uasm_i_##op' macro functions for the microMIPS version.
A pure microMIPS kernel will have the standard macros with
'CL_uasm_i_##op' macro functions for the classic version.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill
8fe4bb98e4 MIPS: microMIPS: Fix incorrect mask for jump immediate.
Jump or branch target addresses have the first bit set. The
original mask did not take this into account and will cause
a field overflow warning for the target address when a jump
immediate instruction is built.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Sanjay Lal
50c8308538 KVM/MIPS32: Binary patching of select privileged instructions.
Currently, the following instructions are translated:
- CACHE (indexed)
- CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations,
  but still much faster than a trap.
- mfc0/mtc0: the virtual COP0 registers for the guest are implemented as
  2-D array.
  [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0.
  mfc0/mtc0 operations are transformed to load/stores.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09 17:48:22 +02:00
Steven Miao
5ae89ee043 bfin cache: dcplb map: add 16M dcplb map for BF60x
use 16M data cplb map on BF60x to avoid too much dcplb miss overhead
cleanup cplb info

Signed-off-by: Steven Miao <realmz6@gmail.com>
2013-05-09 18:22:45 +08:00
Paolo Bonzini
326f578f7e KVM: emulator: emulate SALC
This is an almost-undocumented instruction available in 32-bit mode.
I say "almost" undocumented because AMD documents it in their opcode
maps just to say that it is unavailable in 64-bit mode (sections
"A.2.1 One-Byte Opcodes" and "B.3 Invalid and Reassigned Instructions
in 64-Bit Mode").

It is roughly equivalent to "sbb %al, %al" except it does not
set the flags.  Use fastop to emulate it, but do not use the opcode
directly because it would fail if the host is 64-bit!

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:15:08 +03:00
Paolo Bonzini
7fa57952d7 KVM: emulator: emulate XLAT
This is used by SGABIOS, KVM breaks with emulate_invalid_guest_state=1.
It is just a MOV in disguise, with a funny source address.

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:14:51 +03:00
Paolo Bonzini
a035d5c64d KVM: emulator: emulate AAM
This is used by SGABIOS, KVM breaks with emulate_invalid_guest_state=1.

AAM needs the source operand to be unsigned; do the same in AAD as well
for consistency, even though it does not affect the result.

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:12:58 +03:00
Konrad Rzeszutek Wilk
074d72ff57 x86/microcode: Add local mutex to fix physical CPU hot-add deadlock
This can easily be triggered if a new CPU is added (via
ACPI hotplug mechanism) and from user-space you do:

   echo 1 > /sys/devices/system/cpu/cpu3/online

(or wait for UDEV to do it) on a newly appeared physical CPU.

The deadlock is that the "store_online" in drivers/base/cpu.c
takes the cpu_hotplug_driver_lock() lock, then calls "cpu_up".
"cpu_up" eventually ends up calling "save_mc_for_early"
which also takes the cpu_hotplug_driver_lock() lock.

And here is that lockdep thinks of it:

 smpboot: Stack at about ffff880075c39f44
 smpboot: CPU3: has booted.
 microcode: CPU3 sig=0x206a7, pf=0x2, revision=0x25

 =============================================
 [ INFO: possible recursive locking detected ]
 3.9.0upstream-10129-g167af0e #1 Not tainted
 ---------------------------------------------
 sh/2487 is trying to acquire lock:
  (x86_cpu_hotplug_driver_mutex){+.+.+.}, at: [<ffffffff81075512>] cpu_hotplug_driver_lock+0x12/0x20

 but task is already holding lock:
  (x86_cpu_hotplug_driver_mutex){+.+.+.}, at: [<ffffffff81075512>] cpu_hotplug_driver_lock+0x12/0x20

 other info that might help us debug this:
  Possible unsafe locking scenario:

        CPU0
        ----
   lock(x86_cpu_hotplug_driver_mutex);
   lock(x86_cpu_hotplug_driver_mutex);

  *** DEADLOCK ***

  May be due to missing lock nesting notation

 6 locks held by sh/2487:
  #0:  (sb_writers#5){.+.+.+}, at: [<ffffffff811ca48d>] vfs_write+0x17d/0x190
  #1:  (&buffer->mutex){+.+.+.}, at: [<ffffffff812464ef>] sysfs_write_file+0x3f/0x160
  #2:  (s_active#20){.+.+.+}, at: [<ffffffff81246578>] sysfs_write_file+0xc8/0x160
  #3:  (x86_cpu_hotplug_driver_mutex){+.+.+.}, at: [<ffffffff81075512>] cpu_hotplug_driver_lock+0x12/0x20
  #4:  (cpu_add_remove_lock){+.+.+.}, at: [<ffffffff810961c2>] cpu_maps_update_begin+0x12/0x20
  #5:  (cpu_hotplug.lock){+.+.+.}, at: [<ffffffff810962a7>] cpu_hotplug_begin+0x27/0x60

Suggested-and-Acked-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: fenghua.yu@intel.com
Cc: xen-devel@lists.xensource.com
Cc: stable@vger.kernel.org # for v3.9
Link: http://lkml.kernel.org/r/1368029583-23337-1-git-send-email-konrad.wilk@oracle.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-05-09 11:10:00 +02:00
Vineet Gupta
a690984d60 ARC: [mm] refactor the core (i|d)cache line ops loops
Nothing semantical
* simplify the alignement code by using & operation only
* rename variables clearly as paddr

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 14:18:50 +05:30
Michal Simek
a047775e7e microblaze: Enable IRQ in arch_cpu_idle
Microblaze requires to enable IRQ in cpu_idle loop.

It should be the part of this patch:
"microblaze: Use generic idle loop"
(sha1: e962bb9e9c)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 10:46:16 +02:00
Vineet Gupta
c917a36f5f ARC: [mm] serious bug in vaddr based icache flush
vaddr used to index the cache was clipped from the wrong end, and thus
would potentially fail to flush the correct lines.

The problem was dorment for so long because up until the recent
optimizations it was only used for ptrace break-point only flushes.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 13:45:12 +05:30
Geert Uytterhoeven
b341d84c8a xtensa: Switch to asm-generic/linkage.h
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2013-05-09 01:07:12 -07:00
Chris Zankel
a078ccff56 xtensa: fix redboot load address
With the patch to support MMUv3, the base address for the loaded
binary image has changed, and a fix was applied to the U-Boot image.
This fixes the RedBoot image.

Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:12 -07:00
Max Filippov
efefbcc500 xtensa: ISS: fix timer_lock usage in rs_open
This fixes the following lockdep splat:

[   66.460000] =================================
[   66.460000] [ INFO: inconsistent lock state ]
[   66.460000] 3.9.0-rc5-00161-ga48dd49 #4 Not tainted
[   66.460000] ---------------------------------
[   66.460000] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage.
[   66.460000] swapper/1 [HC0[0]:SC1[1]:HE1:SE0] takes:
[   66.460000]  (timer_lock){+.?...}, at: [<d0006cde>] rs_poll+0x12/0xdc
[   66.460000] {SOFTIRQ-ON-W} state was registered at:
[   66.460000]   [<d00421f0>] lock_acquire+0xec/0x13c
[   66.460000]   [<d01ea036>] _raw_spin_lock+0x3a/0x84
[   66.460000]   [<d0006c8c>] rs_open+0x18/0x58
[   66.460000]   [<d0139ea2>] tty_open+0x262/0x3cc
[   66.460000]   [<d00942e0>] chrdev_open+0x8c/0xe0
[   66.460000]   [<d00907b2>] do_dentry_open$isra$16+0x10e/0x190
[   66.460000]   [<d0091141>] finish_open+0x39/0x48
[   66.460000]   [<d009a0b4>] do_last$isra$34+0x6c4/0x824
[   66.460000]   [<d009a27a>] path_openat+0x66/0x310
[   66.460000]   [<d009a53a>] do_filp_open+0x16/0x44
[   66.460000]   [<d0091445>] do_sys_open+0xd5/0x13c
[   66.460000]   [<d00914be>] sys_open+0x12/0x18
[   66.460000]   [<d0413ffc>] kernel_init_freeable+0xe4/0x12c
[   66.460000]   [<d01e2a9c>] kernel_init+0xc/0x9c
[   66.460000]   [<d00044fc>] ret_from_kernel_thread+0x8/0xc
[   66.460000] irq event stamp: 132542
[   66.460000] hardirqs last  enabled at (132542): [<d01ea2ec>] _raw_spin_unlock_irq+0x30/0x44
[   66.460000] hardirqs last disabled at (132541): [<d01ea11e>] _raw_spin_lock_irq+0xe/0x8c
[   66.460000] softirqs last  enabled at (132234): [<d0017d32>] __do_softirq+0x216/0x2a4
[   66.460000] softirqs last disabled at (132539): [<d0018024>] irq_exit+0x38/0x40
[   66.460000]
[   66.460000] other info that might help us debug this:
[   66.460000]  Possible unsafe locking scenario:
[   66.460000]
[   66.460000]        CPU0
[   66.460000]        ----
[   66.460000]   lock(timer_lock);
[   66.460000]   <Interrupt>
[   66.460000]     lock(timer_lock);
[   66.460000]
[   66.460000]  *** DEADLOCK ***
[   66.460000]
[   66.460000] 1 lock held by swapper/1:
[   66.460000]  #0:  (((&serial_timer))){+.-...}, at: [<d001c65c>] call_timer_fn+0x0/0x1f0
[   66.460000]
Stack: d7c2fac0 00000018 00000004 00000001 d7c2faa0 00000004 00000006 d7c2fa90
       9003e87c d7c2fae0 d7c30000 d025a87c 00000001 0000000f 00000000 d7c2fac0
       9004005d d7c2fb10 d7c30000 d7c30338 00000001 00000001 00000000 d7c30338
[   66.460000] Call Trace:
[   66.460000]  [<d01e4f93>] print_usage_bug$part$26+0x1c3/0x1c8
[   66.460000]  [<d003e87c>] mark_lock+0x2b4/0x440
[   66.460000]  [<d004005d>] __lock_acquire+0x54d/0x16c4
[   66.460000]  [<d00421f0>] lock_acquire+0xec/0x13c
[   66.460000]  [<d01ea036>] _raw_spin_lock+0x3a/0x84
[   66.460000]  [<d0006cde>] rs_poll+0x12/0xdc
[   66.460000]  [<d001c71a>] call_timer_fn+0xbe/0x1f0
[   66.460000]  [<d001cd90>] run_timer_softirq+0x198/0x1f4
[   66.460000]  [<d0017c30>] __do_softirq+0x114/0x2a4
[   66.460000]  [<d0018024>] irq_exit+0x38/0x40
[   66.460000]  [<d00046c0>] do_IRQ+0x44/0x48
[   66.460000]  [<d0005c58>] do_interrupt+0x4c/0x54
[   66.460000]  [<d0003c80>] common_exception_return+0x0/0x5c
[   66.460000]  [<d006682c>] free_pcppages_bulk+0x254/0x308
[   66.460000]

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov
895666a992 xtensa: disable IRQs while IRQ handler is running
IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.

This was overlooked in the commit
  2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.

do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov
8f371c7521 xtensa: enable lockdep support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov
031d0112d7 xtensa: fix arch_irqs_disabled_flags implementation
IRQs are disabled when PS.EXCM is set or PS.INTLEVEL is equal to or
higher than LOCKLEVEL.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov
c92931b200 xtensa: add irq flags trace support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov
3ae908c99e xtensa: provide custom CALLER_ADDR* implementations
Definition of CALLER_ADDR* through __builtin_return_address makes
compiler insert calls to __xtensa_libgcc_window_spill, which in turn
makes fast_syscall_spill_registers syscall that clobbers registers when
called from the kernel mode, leading to invalid opcode exceptions on
return to userspace.

Provide definition for CALLER_ADDR0 as MAKE_PC_FROM_RA(a0, a1) and in
case CONFIG_FRAME_POINTER is enabled extract CALLER_ADDR{1-3} from
stack.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov
3e4196a5cc xtensa: add stacktrace support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov
4e96274e2b xtensa: clean up stpill_registers
- remove unused asm parameters;
- fix EXCM bit setting in the PS SR during _spill_registers call.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov
f4b93ba931 xtensa: don't use a7 in simcalls
To support FRAME_POINTER avoid using a7 in __simc (none of the existing
simcalls needs it). Replace calls to __simc with more specific
simc_read, simc_write and simc_lseek calls.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov
0f7f931027 xtensa: don't attempt to use unconfigured timers
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov
b06c14e5c1 xtensa: provide default platform_pcibios_init implementation
This fixes the following build error:

  arch/xtensa/kernel/built-in.o:(.init.literal+0xe8): undefined reference
	to `platform_pcibios_init'
  arch/xtensa/kernel/built-in.o: In function `setup_arch':
  (.init.text+0x20e): undefined reference to `platform_pcibios_init'

and allows platform to omit definition of platform_pcibios_init if it's
empty.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Paul Bolle
5e44fd012b xtensa: remove KCORE_ELF again
The Kconfig symbol KCORE_ELF was removed in v2.6.0, but reappeared in two
architectures. It is useless. Remove it again.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov
e85e335f8f xtensa: add MMU v3 support
MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:

Way 6 (512 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0x00000000  0x00000000  0x01  0x03 RWX Bypass
        0x20000000  0x20000000  0x01  0x03 RWX Bypass
        0x40000000  0x40000000  0x01  0x03 RWX Bypass
        0x60000000  0x60000000  0x01  0x03 RWX Bypass
        0x80000000  0x80000000  0x01  0x03 RWX Bypass
        0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
        0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
        0xe0000000  0xe0000000  0x01  0x03 RWX Bypass

This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:

Way 5 (128 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xd0000000  0x00000000  0x01  0x07 RWX WB
        0xd8000000  0x00000000  0x01  0x03 RWX Bypass
Way 6 (256 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xe0000000  0xf0000000  0x01  0x07 RWX WB
        0xf0000000  0xf0000000  0x01  0x03 RWX Bypass

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov
d83ff0bb82 xtensa: fix ibreakenable register update
Only set the register when there is at least one ibreak register,
otherwise the build fails:
	arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
	for 'wsr' instruction
	arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
	'ibreakenable' for 'wsr' instruction

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov
74f5bf029e xtensa: fix oprofile building as module
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Michal Simek
f663b60f52 microblaze: Fix uaccess_ok macro
Fix access_ok macro no to permit
case where user will try to access
the last address space which is equal
to segment address.

Example:
segment addr = 0xbfff ffff
address = 0xbfff fff0
size = 0x10

Current wrong implementation
0xbfff ffff >= (0xbfff fff0 | 0x10 | (0xbfff fff0 + 0x10))
0xbfff ffff >= (0xbfff fff0        | 0xc000 0000)
0xbfff ffff >= 0xf000 0000
return 0 which is access failed even the combination is valid.
because get_fs().seq returns the last valid address.

This patch fix this problem.

Size equals to zero is valid access.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:32 +02:00
Michal Simek
6dc92c9c3f microblaze: Add support for new cpu versions and target architecture
Update PVR values based on reference manual.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek
08aaefa0df microblaze: Do not select OPT_LIB_ASM by default
This option is valid only for BE systems.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek
5eec2f0228 microblaze: Fix initrd support
Initrd/ramdisk support has been never validated.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek
4323cd48a1 microblaze: Do not use r6 in head.S
r6 stores pointer to ramdisk and shouldn't
be used before it is passed to machine_early_init.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Michal Simek
ef9cb4e19b microblaze: pci: Remove duplicated header
Remove duplicated header.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Dan Christensen
7c2c85137f microblaze: Set the default irq_domain
Register the irq_domain created during initialization as the default so
that device drivers can pass NULL to irq_create_mapping and get a
virtual irq to pass to request_irq.

Signed-off-by: Dan Christensen <opello@opello.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Wei Yongjun
995fb054eb microblaze: pci: Remove duplicated include from pci-common.c
Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Gleb Natapov
8d76c49e9f KVM: VMX: fix halt emulation while emulating invalid guest sate
The invalid guest state emulation loop does not check halt_request
which causes 100% cpu loop while guest is in halt and in invalid
state, but more serious issue is that this leaves halt_request set, so
random instruction emulated by vm86 #GP exit can be interpreted
as halt which causes guest hang. Fix both problems by handling
halt_request in emulation loop.

Reported-by: Tomas Papan <tomas.papan@gmail.com>
Tested-by: Tomas Papan <tomas.papan@gmail.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
CC: stable@vger.kernel.org
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 09:04:56 +03:00
Steven Miao
5b0830914a blackfin: smp: fix smp build after drop asm/system.h
Signed-off-by: Steven Miao <realmz6@gmail.com>
2013-05-09 13:08:45 +08:00
James Cosin
352030530c blackfin: fix bootup core clock and system clock display
From: James Cosin <jkosin@intcomgrp.com>

fixes the number of digits to 6 after the decimal point to regain the
significant 0s in the frequency after the decimal point.

Signed-off-by: Steven Miao <realmz6@gmail.com>
2013-05-09 13:03:32 +08:00
Tony Lindgren
d5a2b34fdd ARM: dts: Configure and fix the McSPI pins for 4430sdp
The bootloader configures the pins, but has pull bits
set without pull enable bits. While this is harmless,
and won't do anything, it seems to cause confusion at
least for me every time looking at the pin configuration.
Fix it for DT based boot.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:17:05 -07:00
Philip Avinash
e45879ec26 ARM: dts: AM33XX: Add GPMC node
Add GPMC data node to AM33XX device tree file.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:17:05 -07:00
Nishanth Menon
45465c5e59 ARM: dts: OMAP4460: Fix CPU OPP voltages
commit d16fb25 (ARM: dts: OMAP4460: Add CPU OPP table)
introduced wrong OPP voltages per OPP by mistake. Sync the OPP
tables with existing OMAP4460 OPP data in
arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:17:05 -07:00
Nishanth Menon
e011cf69c6 ARM: dts: OMAP36xx: Fix CPU OPP voltages
commit 3027e26 (ARM: dts: OMAP36xx: Add CPU OPP table)
introduced wrong OPP voltages per OPP by mistake. Sync the OPP
tables with existing OMAP36xx OPP data in
arch/arm/mach-omap2/opp3xxx_data.c

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:17:05 -07:00
Peter Ujfalusi
827897c05c ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module
Boards supported upstream all use TWL6040 as audio codec, enable the common
ASoC machine driver by default for them.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:07:40 -07:00
Vaibhav Hiremath
d240ef3056 ARM: OMAP2: AM33XX: id: Add support for new AM335x PG2.1 Si
Add support for chip id detection of AM335x PG2.1 Silicon.

Currently omap3xxx_check_revision() detects PG1.0 and PG2.0 only,
this patch extends it by adding PG2.1 Si support.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:07:40 -07:00
Christoph Fritz
27b105bb99 omap: mux: add AM/DM37x gpios
This patch adds GPIO pins found on AM/DM37x.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 17:07:40 -07:00
Tony Lindgren
a8a07fffe4 Merge branch 'omap-gpmc-fixes-for-v3.10' of git://github.com/jonhunter/linux into fixes 2013-05-08 17:06:39 -07:00
Wei Yongjun
348c34225d ARM: OMAP1: DMA: fix error handling in omap1_system_dma_init()
Add the missing iounmap() before return from omap1_system_dma_init()
in the error handling case.
Also removed platform_device_del() on add resources error case which
cause dup device delete.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 16:48:02 -07:00
Kevin Hilman
e7e17c5386 ARM: OMAP2+: omap_device: use late_initcall_sync
If DEBUG_LL and earlyprintk are enabled, and omap-serial.c is compiled
as a module, the kernel boot hangs early as the clocks for serial port
are cut while earlyprintk still uses the port.

The problem is a race between the late_initcall for omap_device (which
idles devices that have no drivers) and the late_initcall in
kernel/printk.c which turns off the earlyconsole.   Any printks
that happen between this omap_device late initcall and the earlyconsole
late initcall will crash when accessing the UART.

The fix is to ensure the omap_device initcall happens after the
earlyconsole initcall.

Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 16:48:01 -07:00
Aaro Koskinen
e65f131a14 ARM: OMAP: RX-51: change probe order of touchscreen and panel SPI devices
Commit 9fdca9df (spi: omap2-mcspi: convert to module_platform_driver)
broke the SPI display/panel driver probe on RX-51/N900. The exact cause is
not fully understood, but it seems to be related to the probe order. SPI
communication to the panel driver (spi1.2) fails unless the touchscreen
(spi1.0) has been probed/initialized before. When the omap2-mcspi driver
was converted to a platform driver, it resulted in that the devices are
probed immediately after the board registers them in the order they are
listed in the board file.

Fix the issue by moving the touchscreen before the panel in the SPI
device list.

The patch fixes the following failure:

[    1.260955] acx565akm spi1.2: invalid display ID
[    1.265899] panel-acx565akm display0: acx_panel_probe panel detect error
[    1.273071] omapdss CORE error: driver probe failed: -19

Tested-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Joni Lapilainen <joni.lapilainen@gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: stable@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 16:48:00 -07:00
Roger Quadros
cf7dd65811 ARM: OMAP3: Beagle: Fix USB Host on beagle xM Ax/Bx
On Beagle xM Rev. Ax/Bx, the USB power enable GPIO logic is
reversed when compared to other revisions i.e. it is
active high instead of active low.

Use the beagle_config.usb_pwr_level flag correctly so that
the power regulator can be configured at runtime.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 16:48:00 -07:00
Linus Torvalds
3d15b798ea - Since drivers/irqchip/irq-gic.c no longer has dependencies on arm32
specifics (the 'gic' branch merged), it can be enabled on arm64.
 - Enable arm64 support for poweroff/restart (for code under
   drivers/power/reset/).
 - Fixes (dts file, exception handling, bitops)
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Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

Pull arm64 update from Catalin Marinas:

 - Since drivers/irqchip/irq-gic.c no longer has dependencies on arm32
   specifics (the 'gic' branch merged), it can be enabled on arm64.

 - Enable arm64 support for poweroff/restart (for code under
   drivers/power/reset/).

 - Fixes (dts file, exception handling, bitops)

* tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
  arm64: Treat the bitops index argument as an 'int'
  arm64: Ignore the 'write' ESR flag on cache maintenance faults
  arm64: dts: fix #address-cells for foundation-v8
  arm64: vexpress: Add support for poweroff/restart
  arm64: Enable support for the ARM GIC interrupt controller
2013-05-08 15:15:27 -07:00
Linus Torvalds
246e6a0d78 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel
Pull Hexagon fixes from Richard Kuo:
 "A bug fix and a Kconfig cleanup"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel:
  HEXAGON: Remove non existent reference to GENERIC_KERNEL_EXECVE & GENERIC_KERNEL_THREAD
  Hexagon: fix register used to call do_work_pending
2013-05-08 15:08:59 -07:00
Jon Hunter
e60f18d6bc ARM: dts: OMAP4: Fix ethernet IRQ for OMAP4 boards
Commit ff5c9059 (ARM: dts: OMAP3+: Correct gpio #interrupts-cells
property) updated the number of interrupt cells required for configuring
gpios as interrupts for other devices (such as ethernet controllers).
This update allowed the interrupt type (edge, level, etc) to be
configured via device-tree (as described in the
Documentation/devicetree/bindings/gpio/gpio-omap.txt).

This broke ethernet support on the OMAP4 SDP board that defines a gpio
as the ethernet IRQ because the interrupt type (level, edge, etc) was
not getting configured correctly. This board use the ks8851 ethernet
chip which has an active low interrupt. Fix this by defining the gpio
interrupt as active-low in the device-tree binding.

Please note that the OMAP4-VAR-SOM also uses the same ethernet
controller and it is expected it will have the same problem. So the
same fix is also applied to this board.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-05-08 15:03:35 -07:00
Zhenzhong Duan
4ea9b9aca9 xen: mask x2APIC feature in PV
On x2apic enabled pvm, doing sysrq+l, got NULL pointer dereference as below.

    SysRq : Show backtrace of all active CPUs
    BUG: unable to handle kernel NULL pointer dereference at           (null)
    IP: [<ffffffff8125e3cb>] memcpy+0xb/0x120
    Call Trace:
     [<ffffffff81039633>] ? __x2apic_send_IPI_mask+0x73/0x160
     [<ffffffff8103973e>] x2apic_send_IPI_all+0x1e/0x20
     [<ffffffff8103498c>] arch_trigger_all_cpu_backtrace+0x6c/0xb0
     [<ffffffff81501be4>] ? _raw_spin_lock_irqsave+0x34/0x50
     [<ffffffff8131654e>] sysrq_handle_showallcpus+0xe/0x10
     [<ffffffff8131616d>] __handle_sysrq+0x7d/0x140
     [<ffffffff81316230>] ? __handle_sysrq+0x140/0x140
     [<ffffffff81316287>] write_sysrq_trigger+0x57/0x60
     [<ffffffff811ca996>] proc_reg_write+0x86/0xc0
     [<ffffffff8116dd8e>] vfs_write+0xce/0x190
     [<ffffffff8116e3e5>] sys_write+0x55/0x90
     [<ffffffff8150a242>] system_call_fastpath+0x16/0x1b

That's because apic points to apic_x2apic_cluster or apic_x2apic_phys
but the basic element like cpumask isn't initialized.

Mask x2APIC feature in pvm to avoid overwrite of apic pointer,
update commit message per Konrad's suggestion.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@oracle.com>
Tested-by: Tamon Shiose <tamon.shiose@oracle.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2013-05-08 08:38:11 -04:00
Konrad Rzeszutek Wilk
cb91f8f44c xen/spinlock: Fix check from greater than to be also be greater or equal to.
During review of git commit cb9c6f15f3
("xen/spinlock:  Check against default value of -1 for IRQ line.")
Stefano pointed out a bug in the patch. Unfortunatly due to vacation
timing the fix was not applied and this patch fixes it up.

Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2013-05-08 08:38:09 -04:00
Konrad Rzeszutek Wilk
d5b17dbff8 xen/smp/pvhvm: Don't point per_cpu(xen_vpcu, 33 and larger) to shared_info
As it will point to some data, but not event channel data (the
shared_info has an array limited to 32).

This means that for PVHVM guests with more than 32 VCPUs without
the usage of VCPUOP_register_info any interrupts to VCPUs
larger than 32 would have gone unnoticed during early bootup.

That is OK, as during early bootup, in smp_init we end up calling
the hotplug mechanism (xen_hvm_cpu_notify) which makes the
VCPUOP_register_vcpu_info call for all VCPUs and we can receive
interrupts on VCPUs 33 and further.

This is just a cleanup.

Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2013-05-08 08:38:08 -04:00
Steven J. Hill
f6b06d9361 MIPS: microMIPS: Support dynamic ASID sizing.
Changes for pure microMIPS cores to dynamically determine the ASID
size at boot time.

Includes bug fix https://patchwork.linux-mips.org/patch/5230/

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
2013-05-08 12:30:10 +02:00
Steven J. Hill
d532f3d267 MIPS: Allow ASID size to be determined at boot time.
Original patch by Ralf Baechle and removed by Harold Koerfgen
with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This
allows for more generic kernels since the size of the ASID
and corresponding masks can be determined at run-time. This
patch is also required for the new Aptiv cores and has been
tested on Malta and Malta Aptiv platforms.

[ralf@linux-mips.org: Added relevant part of fix
https://patchwork.linux-mips.org/patch/5213/]

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 12:30:10 +02:00
Steven J. Hill
49bffbdc88 MIPS: FW: malta: Code formatting clean-ups.
Clean-up code according to the 'checkpatch.pl' script.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:10 +02:00
Steven J. Hill
270690e00c MIPS: FW: Remove obsolete header file for MTI platforms.
Remove 'arch/mips/include/asm/mips-boards/prom.h' and get rid of
all inclusions of it by Malta and SEAD-3 platforms.

[ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS:
ar7 powertv build"].

[ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS:
unbreak powertv build"].

[ralf@linux-mips.org: Test. Build. Your. Fscking. Code. Or...]

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:10 +02:00
Steven J. Hill
b431f09d55 MIPS: FW: malta: Use new common FW library variable processing.
Remove old YAMON prom code and use common firmware library code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:09 +02:00
Steven J. Hill
0be2abbcee MIPS: FW: sead3: Use new common FW library variable processing.
Remove old YAMON prom code and use common firmware library code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:09 +02:00
Steven J. Hill
14aecdd419 MIPS: FW: Add environment variable processing.
Add parsing of the environment and command line variables passed to
the kernel to the firmware library.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:09 +02:00
Steven J. Hill
98ffcf602b MIPS: Add declarations to MIPS Technologies Inc. generic header.
Add declaration of 'mips_scroll_message' and 'mips_display_message'
to the common generic header file for the MIPS Technologies Inc.
development boards.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:09 +02:00
Lars-Peter Clausen
f4d1f2bed6 MIPS: sead3: Use generic suspend/resume for LEDs.
Setting the LED_CORE_SUSPENDRESUME flag causes the LED driver core to call
led_classdev_suspend/led_classdev_resume during suspend/resume. Since this is
exactly what the driver's custom suspend/resume callbacks do we can replace them
by setting the LED_CORE_SUSPENDRESUME flag.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-08 12:30:09 +02:00
Marcelo Tosatti
42bdf991f4 KVM: x86: fix maintenance of guest/host xcr0 state
Emulation of xcr0 writes zero guest_xcr0_loaded variable so that
subsequent VM-entry reloads CPU's xcr0 with guests xcr0 value.

However, this is incorrect because guest_xcr0_loaded variable is
read to decide whether to reload hosts xcr0.

In case the vcpu thread is scheduled out after the guest_xcr0_loaded = 0
assignment, and scheduler decides to preload FPU:

switch_to
{
  __switch_to
    __math_state_restore
      restore_fpu_checking
        fpu_restore_checking
          if (use_xsave())
              fpu_xrstor_checking
		xrstor64 with CPU's xcr0 == guests xcr0

Fix by properly restoring hosts xcr0 during emulation of xcr0 writes.

Analyzed-by: Ulrich Obergfell <uobergfe@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-08 12:47:43 +03:00
Catalin Marinas
420c158dcf arm64: Treat the bitops index argument as an 'int'
The bitops prototype use an 'int' as the bit index type but the asm
implementation assume it to be a 'long'. Since the compiler does not
guarantee zeroing the upper 32-bits in a register when used as 'int',
change the bitops implementation accordingly.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-05-08 10:33:17 +01:00
Catalin Marinas
0e7f7bcc3f arm64: Ignore the 'write' ESR flag on cache maintenance faults
ESR.WnR bit is always set on data cache maintenance faults even though
the page is not required to have write permission. If a translation
fault (page not yet mapped) happens for read-only user address range,
Linux incorrectly assumes a permission fault. This patch adds the check
of the ESR.CM bit during the page fault handling to ignore the 'write'
flag.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Tim Northover <Tim.Northover@arm.com>
Cc: stable@vger.kernel.org
2013-05-08 10:33:16 +01:00
Mark Rutland
ed1f23637a arm64: dts: fix #address-cells for foundation-v8
Commit 90556ca1 ("arm64: vexpress: Add dts files for the ARMv8 RTSM
models") added foundation-v8.dts, but erroneously set
/cpus/#address-cells = <1> while providing two cells in each cpus/cpu@N
node's reg property.

As of commit ea393a2e ("arm64: smp: honour #address-size when parsing
CPU reg property") we read in as many address cells as specified rather
than always reading two. This means that for foundation-v8.dts, we only
read the first reg cell (zero) for each cpu node, and receive a lot of
warnings at boot of the form "/cpus/cpu@1: duplicate cpu reg properties
in the DT".

This patch corrects foundation-v8.dts to have the correct value for
/cpus/#address-cells.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-05-08 10:23:01 +01:00
Catalin Marinas
aa1e8ec1d2 arm64: vexpress: Add support for poweroff/restart
This patch adds the arm_pm_poweroff definition expected by the
vexpress-poweroff.c driver and enables the latter for arm64.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
2013-05-08 10:23:00 +01:00
Catalin Marinas
c4188edc9e arm64: Enable support for the ARM GIC interrupt controller
This patch enables ARM_GIC on the arm64 kernel.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-05-08 10:22:59 +01:00
Catalin Marinas
e6b6dc7f35 Merge branch 'gic' into HEAD
* arm64-prep-gic:
  irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
  irqchip: gic: Call handle_bad_irq() directly
  arm: Move chained_irq_(enter|exit) to a generic file
  arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
2013-05-08 10:22:07 +01:00
Benjamin Herrenschmidt
1de1455f33 powerpc/powernv: Properly drop characters if console is closed
If the firmware returns an error such as "closed" (or hardware
error), we should drop characters.

Currently we only do that when a firmware compatible with OPAL v2
APIs is detected, in the code that calls opal_console_write_buffer_space(),
which didn't exist with OPAL v1 (or didn't work).

However, when enabling early debug consoles, the flag indicating
that v2 is supported isn't set yet, causing us, in case of errors
or closed console, to spin forever.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-05-08 14:14:26 +10:00
Linus Torvalds
5af43c24ca Merge branch 'akpm' (incoming from Andrew)
Merge more incoming from Andrew Morton:

 - Various fixes which were stalled or which I picked up recently

 - A large rotorooting of the AIO code.  Allegedly to improve
   performance but I don't really have good performance numbers (I might
   have lost the email) and I can't raise Kent today.  I held this out
   of 3.9 and we could give it another cycle if it's all too late/scary.

I ended up taking only the first two thirds of the AIO rotorooting.  I
left the percpu parts and the batch completion for later.  - Linus

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (33 commits)
  aio: don't include aio.h in sched.h
  aio: kill ki_retry
  aio: kill ki_key
  aio: give shared kioctx fields their own cachelines
  aio: kill struct aio_ring_info
  aio: kill batch allocation
  aio: change reqs_active to include unreaped completions
  aio: use cancellation list lazily
  aio: use flush_dcache_page()
  aio: make aio_read_evt() more efficient, convert to hrtimers
  wait: add wait_event_hrtimeout()
  aio: refcounting cleanup
  aio: make aio_put_req() lockless
  aio: do fget() after aio_get_req()
  aio: dprintk() -> pr_debug()
  aio: move private stuff out of aio.h
  aio: add kiocb_cancel()
  aio: kill return value of aio_complete()
  char: add aio_{read,write} to /dev/{null,zero}
  aio: remove retry-based AIO
  ...
2013-05-07 20:49:51 -07:00
Kent Overstreet
a27bb332c0 aio: don't include aio.h in sched.h
Faster kernel compiles by way of fewer unnecessary includes.

[akpm@linux-foundation.org: fix fallout]
[akpm@linux-foundation.org: fix build]
Signed-off-by: Kent Overstreet <koverstreet@google.com>
Cc: Zach Brown <zab@redhat.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Mark Fasheh <mfasheh@suse.com>
Cc: Joel Becker <jlbec@evilplan.org>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Asai Thambi S P <asamymuthupa@micron.com>
Cc: Selvan Mani <smani@micron.com>
Cc: Sam Bradshaw <sbradshaw@micron.com>
Cc: Jeff Moyer <jmoyer@redhat.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Benjamin LaHaise <bcrl@kvack.org>
Reviewed-by: "Theodore Ts'o" <tytso@mit.edu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-05-07 20:16:25 -07:00
Sanjay Lal
82d45de655 MIPS: Export symbols used by KVM/MIPS module
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:37 +02:00
Sanjay Lal
12e25f8e19 MIPS: ASM offsets for VCPU arch specific fields.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:37 +02:00
Sanjay Lal
f9afbd45b0 MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a ASID wrap.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:36 +02:00
Sanjay Lal
f2e3656d23 MIPS: Export routines needed by the KVM module.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:36 +02:00
Sanjay Lal
f5c236dd0a KVM/MIPS32: Routines to handle specific traps/exceptions while executing the guest.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:36 +02:00
Sanjay Lal
06d1838db0 KVM/MIPS32: Guest interrupt delivery.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:36 +02:00
Sanjay Lal
3c20ef5262 KVM/MIPS32: COP0 accesses profiling.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:36 +02:00
Sanjay Lal
03a0331c8c KVM/MIPS32: Release notes and KVM module Makefile
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:35 +02:00
Sanjay Lal
858dd5d457 KVM/MIPS32: MMU/TLB operations for the Guest.
- Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are
loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while
manipulating TLBs.
- Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries.
- Shadow TLBs map Guest virtual addresses to Host physical addresses.

    - TLB miss handling details:
        Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest.
        Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000)
            Lookup in Guest/Virtual TLB
            If an entry doesn’t match
                deliver appropriate TLBMISS LD/ST exception to the guest
            If entry does exist in the Guest TLB and is NOT Valid
                Deliver TLB invalid exception to the guest
            If entry does exist in the Guest TLB and is VALID
                Inject the TLB entry into the Shadow TLB

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:35 +02:00
Sanjay Lal
e685c689f3 KVM/MIPS32: Privileged instruction/target branch emulation.
- The Guest kernel is run in UM and privileged instructions cause a trap.
- If the instruction causing the trap is in a branch delay slot, the branch
  needs to be emulated to figure out the PC @ which the guest will resume
  execution.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:35 +02:00
Sanjay Lal
9843b030cc KVM/MIPS32: KVM Guest kernel support.
Both Guest kernel and Guest Userspace execute in UM. The memory map is as follows:
Guest User address space:   0x00000000 -> 0x40000000
Guest Kernel Unmapped:      0x40000000 -> 0x60000000
Guest Kernel Mapped:        0x60000000 -> 0x80000000
- Guest Usermode virtual memory is limited to 1GB.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:35 +02:00
Sanjay Lal
669e846e6c KVM/MIPS32: MIPS arch specific APIs for KVM
- Implements the arch specific APIs for KVM, some are stubs for MIPS
- kvm_mips_handle_exit(): Main 'C' distpatch routine for handling exceptions while in "Guest" mode.
- Also implements in-kernel timer interrupt support for the guest.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:35 +02:00
Sanjay Lal
b680f70fc1 KVM/MIPS32: Entry point for trampolining to the guest and trap handlers.
- __kvm_mips_vcpu_run: main entry point to enter guest, we save kernel context, load
  up guest context from and ERET to guest context.
- mips32_exception: L1 exception handler(s), save k0/k1 and jump to main handlers.
- mips32_GuestException: Generic exception handlers for exceptions/interrupts while in
  guest context.  Save guest context, restore some kernel context and jump to
  main 'C' handler: kvm_mips_handle_exit()

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:34 +02:00
Sanjay Lal
740765ce45 KVM/MIPS32: Arch specific KVM data structures.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:34 +02:00
Sanjay Lal
2235a54dea KVM/MIPS32: Infrastructure/build files.
- Add the KVM option to MIPS build files.
- Add default config files for KVM host/guest kernels.
- Change the link address for the Malta KVM Guest kernel to UM (0x40100000).
- Add KVM Kconfig file with KVM/MIPS specific options

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:55:34 +02:00
Ralf Baechle
fc0460d0df MIPS: IP27: Remove pfn_t.
In the Linux kernel traditionally pfns are represented by an unsigned long.
However a few bits of the SGI IP27 platform code that were ported from
IRIX are using pfn_t for historic reasons.  This is conflicting with
KVM's use of pfn_t.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08 03:51:58 +02:00
Zhao Hongjiang
1ab4ce7623 parisc: remove the second argument of kmap_atomic()
kmap_atomic() requires only one argument now.

Signed-off-by: Zhao Hongjiang <zhaohongjiang@huawei.com>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: Rolf Eike Beer <eike-kernel@sf-tec.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-05-07 18:38:27 -07:00
Jiang Liu
70affe4520 mm/SPARC: use common help functions to free reserved pages
Use common help functions to free reserved pages.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-05-07 18:38:26 -07:00
Linus Torvalds
9affd6becb arm: fix mismerge of arch/arm/mach-omap2/timer.c
I badly screwed up the merge in commit 6fa52ed33b ("Merge tag
'drivers-for-linus' of git://git.kernel.org/pub/.../arm-soc") by
incorrectly taking the arch/arm/mach-omap2/* data fully from the merge
target because the 'drivers-for-linus' branch seemed to be a proper
superset of the duplicate ARM commits.

That was bogus: commit ff931c821b ("ARM: OMAP: clocks: Delay clk inits
atleast until slab is initialized") only existed in head, and the
changes to arch/arm/mach-omap2/timer.c from that commit got list.

Re-doing the merge more carefully, I do think this part was the only
thing I screwed up.  Knock wood.

Reported-by: Tony Lindgren <tony@atomide.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-05-07 17:59:53 -07:00
Ralf Baechle
9b3539e0e5 Merge branch 'mips-next-3.10' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next 2013-05-08 01:27:46 +02:00
Jonas Gorski
1cd1c04927 MIPS: BCM63XX: add missing clocks for BCM6328 and BCM6362
Add some mosty unused, but missing clocks for BCM6328 and BCM6362.
This also fixes PCIe init on BCM6362.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5200/
Acked-by: John Crispin <blogic@openwrt.org>
2013-05-08 01:19:12 +02:00
John Crispin
9b75733b7b MIPS: ath79: make use of the new memory detection code
There is now a generic function for detecting memory size. Use this instead of
the one found in the ath79 support.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5149/
2013-05-08 01:19:12 +02:00
John Crispin
dd63b00804 MIPS: ralink: make use of the new memory detection code
Call detect_memory_region() from plat_mem_setup() unless the size was already
read from the system controller.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5184/
2013-05-08 01:19:12 +02:00
John Crispin
51e3960784 MIPS: ralink: add memory definition for MT7620
Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5183/
2013-05-08 01:19:12 +02:00
John Crispin
fe98f612a1 MIPS: ralink: add memory definition for RT3883
Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5182/
2013-05-08 01:19:12 +02:00
John Crispin
38d5b81cde MIPS: ralink: add memory definition for RT2880
Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5181/
2013-05-08 01:19:11 +02:00
John Crispin
dafecee8bb MIPS: ralink: add memory definition for RT305x
Populate struct soc_info with the data that describes our RAM window.

As memory detection fails on RT5350 we read the amount of available memory
from the system controller.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5180/
2013-05-08 01:19:11 +02:00
John Crispin
629e39eec8 MIPS: ralink: add memory definition to struct ralink_soc_info
Depending on the actual SoC we have a different base address as well as minimum
and maximum size for RAM. Add these fields to the per SoC structure.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5179/
2013-05-08 01:19:11 +02:00
John Crispin
4d9f77d252 MIPS: add detect_memory_region()
Add a generic way of detecting the available RAM. This function is based on the
implementation already used by ath79.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5178/
2013-05-08 01:19:11 +02:00
John Crispin
9d50094dfe DT: MIPS: ralink: add MT7620A dts files
Add a dtsi file for MT7620A SoC and a sample dts file.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5190/
2013-05-08 01:19:11 +02:00
John Crispin
6fbfe90e58 DT: MIPS: ralink: add RT3883 dts files
Add a dtsi file for RT3883 SoC and a sample dts file.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5189/
2013-05-08 01:19:11 +02:00
John Crispin
d99e19c799 DT: MIPS: ralink: add RT2880 dts files
Add a dtsi file for RT2880 SoC and a sample dts file.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5188/
2013-05-08 01:19:10 +02:00
John Crispin
da5b4cfa54 DT: MIPS: ralink: clean up RT3050 dtsi and dts file
* remove nodes for cores whose drivers are not upstream yet
* add compat string for an additional soc
* fix a whitespace error

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5186/
2013-05-08 01:19:10 +02:00
Gabor Juhos
de3eb02a53 MIPS: ralink: add cpu-feature-overrides.h
Add cpu-feature-overrides.h for RT288x, RT305x and RT3883.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5175/
2013-05-08 01:19:10 +02:00
John Crispin
594bde683d MIPS: ralink: adds support for MT7620 SoC family
Add support code for mt7620 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-05-08 01:19:09 +02:00
John Crispin
293840b999 MIPS: ralink: adds support for RT3883 SoC family
Add support code for rt3883 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5185/
2013-05-08 01:19:09 +02:00