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MIPS: microMIPS: Add unaligned access support.
Add logic needed to handle unaligned accesses in microMIPS mode. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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@ -7,6 +7,7 @@
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* Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004 Thiemo Seufer
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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@ -243,34 +244,115 @@ struct mips_frame_info {
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static inline int is_ra_save_ins(union mips_instruction *ip)
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{
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#ifdef CONFIG_CPU_MICROMIPS
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union mips_instruction mmi;
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/*
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* swsp ra,offset
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* swm16 reglist,offset(sp)
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* swm32 reglist,offset(sp)
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* sw32 ra,offset(sp)
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* jradiussp - NOT SUPPORTED
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*
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* microMIPS is way more fun...
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*/
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if (mm_insn_16bit(ip->halfword[0])) {
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mmi.word = (ip->halfword[0] << 16);
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return ((mmi.mm16_r5_format.opcode == mm_swsp16_op &&
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mmi.mm16_r5_format.rt == 31) ||
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(mmi.mm16_m_format.opcode == mm_pool16c_op &&
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mmi.mm16_m_format.func == mm_swm16_op));
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}
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else {
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mmi.halfword[0] = ip->halfword[1];
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mmi.halfword[1] = ip->halfword[0];
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return ((mmi.mm_m_format.opcode == mm_pool32b_op &&
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mmi.mm_m_format.rd > 9 &&
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mmi.mm_m_format.base == 29 &&
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mmi.mm_m_format.func == mm_swm32_func) ||
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(mmi.i_format.opcode == mm_sw32_op &&
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mmi.i_format.rs == 29 &&
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mmi.i_format.rt == 31));
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}
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#else
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/* sw / sd $ra, offset($sp) */
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return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
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ip->i_format.rs == 29 &&
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ip->i_format.rt == 31;
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#endif
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}
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static inline int is_jal_jalr_jr_ins(union mips_instruction *ip)
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{
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#ifdef CONFIG_CPU_MICROMIPS
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/*
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* jr16,jrc,jalr16,jalr16
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* jal
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* jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
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* jraddiusp - NOT SUPPORTED
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*
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* microMIPS is kind of more fun...
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*/
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union mips_instruction mmi;
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mmi.word = (ip->halfword[0] << 16);
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if ((mmi.mm16_r5_format.opcode == mm_pool16c_op &&
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(mmi.mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) ||
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ip->j_format.opcode == mm_jal32_op)
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return 1;
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if (ip->r_format.opcode != mm_pool32a_op ||
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ip->r_format.func != mm_pool32axf_op)
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return 0;
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return (((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op);
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#else
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if (ip->j_format.opcode == jal_op)
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return 1;
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if (ip->r_format.opcode != spec_op)
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return 0;
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return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
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#endif
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}
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static inline int is_sp_move_ins(union mips_instruction *ip)
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{
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#ifdef CONFIG_CPU_MICROMIPS
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/*
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* addiusp -imm
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* addius5 sp,-imm
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* addiu32 sp,sp,-imm
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* jradiussp - NOT SUPPORTED
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*
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* microMIPS is not more fun...
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*/
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if (mm_insn_16bit(ip->halfword[0])) {
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union mips_instruction mmi;
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mmi.word = (ip->halfword[0] << 16);
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return ((mmi.mm16_r3_format.opcode == mm_pool16d_op &&
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mmi.mm16_r3_format.simmediate && mm_addiusp_func) ||
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(mmi.mm16_r5_format.opcode == mm_pool16d_op &&
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mmi.mm16_r5_format.rt == 29));
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}
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return (ip->mm_i_format.opcode == mm_addiu32_op &&
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ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29);
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#else
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/* addiu/daddiu sp,sp,-imm */
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if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
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return 0;
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if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op)
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return 1;
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#endif
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return 0;
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}
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static int get_frame_info(struct mips_frame_info *info)
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{
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#ifdef CONFIG_CPU_MICROMIPS
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union mips_instruction *ip = (void *) (((char *) info->func) - 1);
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#else
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union mips_instruction *ip = info->func;
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#endif
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unsigned max_insns = info->func_size / sizeof(union mips_instruction);
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unsigned i;
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@ -290,7 +372,26 @@ static int get_frame_info(struct mips_frame_info *info)
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break;
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if (!info->frame_size) {
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if (is_sp_move_ins(ip))
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{
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#ifdef CONFIG_CPU_MICROMIPS
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if (mm_insn_16bit(ip->halfword[0]))
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{
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unsigned short tmp;
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if (ip->halfword[0] & mm_addiusp_func)
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{
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tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2);
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info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0));
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} else {
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tmp = (ip->halfword[0] >> 1);
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info->frame_size = -(signed short)(tmp & 0xf);
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}
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ip = (void *) &ip->halfword[1];
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ip--;
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} else
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#endif
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info->frame_size = - ip->i_format.simmediate;
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}
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continue;
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}
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if (info->pc_offset == -1 && is_ra_save_ins(ip)) {
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