linux_dsm_epyc7002

mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-03-11 23:27:42 +07:00

Author	SHA1	Message	Date
Stephen Boyd	a83fdfae5a	Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and 'clk-ti-flag-fix' into clk-next * clk-davinci: clk: davinci: Remove redundant dev_err calls clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks clk: davinci: New driver for TI DA8XX CFGCHIP clocks dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks clk: davinci: Add platform information for TI DM646x PSC clk: davinci: Add platform information for TI DM644x PSC clk: davinci: Add platform information for TI DM365 PSC clk: davinci: Add platform information for TI DM355 PSC clk: davinci: Add platform information for TI DA850 PSC clk: davinci: Add platform information for TI DA830 PSC clk: davinci: New driver for davinci PSC clocks dt-bindings: clock: New bindings for TI Davinci PSC clk: davinci: Add platform information for TI DM646x PLL clk: davinci: Add platform information for TI DM644x PLL clk: davinci: Add platform information for TI DM365 PLL clk: davinci: Add platform information for TI DM355 PLL clk: davinci: Add platform information for TI DA850 PLL clk: davinci: Add platform information for TI DA830 PLL clk: davinci: New driver for davinci PLL clocks dt-bindings: clock: Add new bindings for TI Davinci PLL clocks * clk-si544: clk: Add driver for the si544 clock generator chip * clk-rockchip: clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 clk: rockchip: Fix error return in phase clock registration clk: rockchip: Correct the behaviour of restoring cached phase clk: rockchip: Fix wrong parents for MMC phase clock for rk3328 clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228 clk: rockchip: Add 1.6GHz PLL rate for rk3399 clk: rockchip: Restore the clock phase after the rate was changed clk: rockchip: Prevent calculating mmc phase if clock rate is zero clk: rockchip: Free the memory on the error path clk: rockchip: document hdmi_phy external input for rk3328 clk: rockchip: add flags for rk3328 dclk_lcdc clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks clk: rockchip: protect all remaining rk3328 interconnect clocks clk: rockchip: export sclk_hdmi_sfc on rk3328 clk: rockchip: remove HCLK_VIO from rk3328 dt header clk: rockchip: fix hclk_vio_niu on rk3328 * clk-uniphier: clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: uniphier: add ethernet clock control support for PXs3 clk: uniphier: add Pro4/Pro5/PXs2 audio system clock * clk-ti-flag-fix: clk: ti: fix flag space conflict with clkctrl clocks clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag	2018-04-06 13:22:06 -07:00
Stephen Boyd	b03781920c	Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next * clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ...	2018-04-06 13:21:57 -07:00
Stephen Boyd	fbc20b8c3c	Merge branches 'clk-mvebu', 'clk-phase', 'clk-nxp', 'clk-mtk2712' and 'clk-qcom-rpmcc' into clk-next * clk-mvebu: clk: mvebu: armada-38x: add support for missing clocks clk: mvebu: cp110: Fix clock tree representation * clk-phase: clk: Don't show the incorrect clock phase clk: update cached phase to respect the fact when setting phase * clk-nxp: clk: lpc32xx: Set name of regmap_config * clk-mtk2712: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clocks for MT2712 * clk-qcom-rpmcc: clk: qcom: rpmcc: Add support to XO buffered clocks	2018-04-06 13:21:52 -07:00
Stephen Boyd	e8121d9867	Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next * clk-spreadtrum: clk: sprd: add RTC gate for SC9860 dt-bindings: clocks: add APB RTC gate for SC9860 * clk-stm32f: clk: stm32: Add clk entry for SDMMC2 on stm32F769 clk: stm32: Add DSI clock for STM32F469 Board clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK * clk-stm32mp1: clk: stm32: add configuration flags for each of the stm32 drivers clk: stm32mp1: add Debug clocks clk: stm32mp1: add MCO clocks clk: stm32mp1: add RTC clock clk: stm32mp1: add Peripheral & Kernel Clocks clk: stm32mp1: add Kernel timers clk: stm32mp1: add Sub System clocks clk: stm32mp1: add Post-dividers for PLL clk: stm32mp1: add PLL clocks clk: stm32mp1: add Source Clocks for PLLs clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators clk: stm32mp1: Introduce STM32MP1 clock driver dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings * clk-hi655x: clk: enable hi655x common clk automatically * clk-gpio: clk: clk-gpio: Allow GPIO to sleep in set/get_parent	2018-04-06 13:21:45 -07:00
Stephen Boyd	caa9f3b7d7	Merge branches 'clk-versatile', 'clk-doc', 'clk-must-check', 'clk-qcom' and 'clk-debugfs' into clk-next * clk-versatile: clk: versatile: Remove WARNs in ->round_rate() clk: versatile: add min/max rate boundaries for vexpress osc clock * clk-doc: Documentation: clk: enable lock is not held for clk_is_enabled API * clk-must-check: clk: add more __must_check for bulk APIs * clk-qcom: clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider() clk: qcom: gcc-msm8996: Mark aggre0 noc clks as critical * clk-debugfs: clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro	2018-04-06 13:21:39 -07:00
Stephen Boyd	15afa044cb	Merge branches 'clk-ti', 'clk-amlogic', 'clk-tegra' and 'clk-samsung' into clk-next * clk-ti: clk: keystone: sci-clk: add support for dynamically probing clocks clk: ti: add support for clock latching to mux clocks clk: ti: add support for clock latching to divider clocks clk: ti: add generic support for clock latching clk: ti: add support for register read-modify-write low-level operation dt-bindings: clock: ti: add latching support to mux and divider clocks * clk-amlogic: (50 commits) clk: meson: Drop unused local variable and add static clk: meson: clean-up clk81 clocks clk: meson: add fdiv clock gates clk: meson: add mpll pre-divider clk: meson: axg: add hifi pll clock clk: meson: axg: add hifi clock bindings clk: meson: add ROUND_CLOSEST to the pll driver clk: meson: add gp0 frac parameter for axg and gxl clk: meson: improve pll driver results with frac clk: meson: remove special gp0 lock loop clk: meson: poke pll CNTL last clk: meson: add fractional part of meson8b fixed_pll clk: meson: use hhi syscon if available clk: meson: remove obsolete cpu_clk clk: meson: rework meson8b cpu clock clk: meson: split divider and gate part of mpll clk: meson: migrate plls clocks to clk_regmap clk: meson: migrate the audio divider clock to clk_regmap clk: meson: migrate mplls clocks to clk_regmap clk: meson: add regmap helpers for parm ... * clk-tegra: clk: tegra: Fix pll_u rate configuration clk: tegra: Specify VDE clock rate clk: tegra20: Correct PLL_C_OUT1 setup clk: tegra: Mark HCLK, SCLK and EMC as critical clk: tegra: MBIST work around for Tegra210 clk: tegra: add fence_delay for clock registers clk: tegra: Add la clock for Tegra210 * clk-samsung: (22 commits) clk: samsung: Mark a few things static clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412 clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices clk: samsung: exynos5420: Add more entries to EPLL rate table clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU clk: samsung: Add Exynos5 sub-CMU clock driver soc: samsung: pm_domains: Add blacklisting clock handling clk: samsung: Add compile time PLL rate validators clk: samsung: s3c2410: Fix PLL rates clk: samsung: exynos7: Fix PLL rates clk: samsung: exynos5433: Fix PLL rates clk: samsung: exynos5260: Fix PLL rates clk: samsung: exynos5250: Fix PLL rates clk: samsung: exynos3250: Fix PLL rates clk: exynos5433: Extend list of available AUD_PLL output frequencies clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk clk: samsung: Add a git tree entry to MAINTAINERS clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe() ...	2018-04-06 13:21:33 -07:00
Tero Kristo	269bd202bc	clk: ti: fix flag space conflict with clkctrl clocks The introduction of support for CLK_SET_RATE_PARENT flag for clkctrl clocks used a generic clock flag, which causes a conflict with the rest of the clkctrl flags, namely the NO_IDLEST flag. This can cause boot failures on certain platforms where this flag is introduced, by omitting the wait for the clockctrl module to be fully enabled before proceeding with rest of the code. Fix this by moving all the clkctrl specific flags to their own bit-range. Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: `49159a9dc3` ("clk: ti: add support for CLK_SET_RATE_PARENT flag") Reported-by: Christophe Lyon <christophe.lyon@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-04-05 15:25:22 -07:00
Kunihiko Hayashi	6f1aa4ef3f	clk: uniphier: add additional ethernet clock lines for Pro4 Pro4 SoC has clock lines for Giga-bit feature and ethernet phy, and these are mandatory to activate the ethernet controller. This adds support for the clock lines. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-04-05 15:03:51 -07:00
Kunihiko Hayashi	54e1f7ee1f	clk: uniphier: add SATA clock control support Add clock control for SATA controller on UniPhier SoCs. This adds support for PXs2, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-04-05 15:03:49 -07:00
Kunihiko Hayashi	2e277efb82	clk: uniphier: add PCIe clock control support Add clock control for PCIe controller on UniPhier SoCs. This adds support for Pro5, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-04-05 15:03:45 -07:00
Stephen Boyd	f6ae7c36e6	Some more fixes for Rockchip clocks mainly resulting from the changes in phase-handling. Which revealed some parent issues on rk3228 and rk3328 as well as additional issue in how handle phase restoration. And to top it off two assignments of already existing clock ids for rk3399. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlq4G6MQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgYQ4CACEAVtwlQcxtg6ycDYqmpwyr8rM266sjuwC gCXUK39OcypYpXUI8kiQA8vJOH+s/JWoGk9Uiv6PirsBxmhO+CoG9Pf4Wpg68T+k MhXAaLSU0l1+EiTtg9yENiObKjn0Ah0KyEwAlMv1bGo5ilAWmnBeQeccc2ghOqEs CB/BtoZ5ECV8sWDG7nWgLQNpmRWL77J9fO4MuoAaYJmd7+EooE/D+roDTFsDxLJF x+SeYvPGzVLKab7nMqdBlM8qHg07+4KR/EtFAaCoH71WqrnN8NizCAVQMftYvu9R yEGJIytNqM5RKArM1HelYZYVuGFmlwRT0RlgfjAi54mZmPrTjr77 =WWY7 -----END PGP SIGNATURE----- Merge tag 'v4.17-rockchip-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull more Rockchip clk driver updates from Heiko Stuebner: Some more fixes for Rockchip clocks mainly resulting from the changes in phase-handling. Which revealed some parent issues on rk3228 and rk3328 as well as additional issue in how handle phase restoration. And to top it off two assignments of already existing clock ids for rk3399. * tag 'v4.17-rockchip-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 clk: rockchip: Fix error return in phase clock registration clk: rockchip: Correct the behaviour of restoring cached phase clk: rockchip: Fix wrong parents for MMC phase clock for rk3328 clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-04-05 13:28:16 -07:00
Mike Looijmans	953cc3e811	clk: Add driver for the si544 clock generator chip This patch adds the driver and devicetree documentation for the Silicon Labs SI544 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 200kHz to 1500MHz. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-23 10:05:25 -07:00
Wei Yongjun	fc3fcb4ff1	clk: davinci: Remove redundant dev_err calls There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-23 09:44:45 -07:00
Stephen Boyd	aa584d28f3	clk: renesas: Updates for v4.17 (take two) - Fix the incorrect display clock on R-Car M3-N, - Always use readl()/writel(), - Small fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJas+E+AAoJEEgEtLw/Ve77zsUP/2pX3Yn/ydkiCzaIhyelGukH /adQ/Bs4jwpltImSBo70qW8p6k6okFaJjy0lunyKRO1rMxu6X9+HMr4Qh2hP/cqz L8QBONxHXOHjiHtpzx7d2SlCGl1TrW5nEAWSJqEuifLIYzxhxxsv1aFkH2wEhLQn P8vgFZMSYeWnMCp/fb0cflmeNuNuGRZQaehUU+9gZQEcPo6pSYohT0ooIvy3OcUA pGB96FtJtUdq0qrZIdHFMv/h2QnZwLBpfFFT1Nl9ATbP/htqxsgH45PZYLqyVgTr F5AtKR/xmMx+P0b+Q8KWAqqfZPtsyPOy/SsBUK49/OeCQsnbZGTWjcRvbSC67y6y VYM+2ve0RSF7oA87+EkKszezNY9H+UJz3G3rzrIaIL+fChshLvjXM5O5YT/oyOxP 4FvxXmcgu1g8qJ3dsXVV6rkR1qsdWKrR4blvqGHB6XHzmeH96mT/znpQUfO6J2rp 9icKL0O9yFMuUe+Lvt7/t+cB16KNOaNrt3/dqgsRfM9Wuch7a1p2XV3MUrreG8FN zd+DJagr4mcHpGS932RMEKqrcpBZUxw+4/VjNxz5GLc90tM11MakaNu9zf0GD3HP GlRcBhckwAX3QgzyH3VrX9KautT4/9XXjMHQFWmjnON2UcZL2LKuGbTahBxpfCc1 PFQ455sXk/jvxFcq2tan =QWlH -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Fix the incorrect display clock on R-Car M3-N, - Always use readl()/writel(), - Small fixes. * tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: renesas: r8a77965: Replace DU2 clock	2018-03-23 09:40:52 -07:00
Kunihiko Hayashi	c2fd8756c5	clk: uniphier: add ethernet clock control support for PXs3 Add clock control for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-23 09:39:36 -07:00
Linus Walleij	726fef09b8	clk: ux500: Drop AB8540/9540 support The AB8540 was an evolved version of the AB8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the AB8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-23 09:36:11 -07:00
Stephen Boyd	26b99db0b6	Allwinner clock changes for 4.17 Our usual bunch of changes for the next merge window. The most significant addition is the support of the H6 clock unit. Other than that, there's a bunch of fixes for the video clocks on the H3 and H5, and some Kconfig cleanup. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAlqz020ACgkQ0rTAlCFN r3SrhQ//dCFkn/8f/KUlZBhdlVBMfZchqAfHKSuN8ie3Khyx5TsF5WW/AzgHrtV/ VOiy89SEO/FHdJSz2P/lUgwzVUmv2+5nTLIDi6L9QASVA6gjsaarthrdhRldSFh6 bMq0PjHL9bsUriazQmYbEPWNRvgIZ2eQtLg1/hTx3E07E3TnipnGGcfIFBB99hol RHNWmVP9lPfqRBQaKjVHWWWDcFG5laKN4axKpEgYP3K0zoIdYVjkjk2yqL+qTpxY waYB2iz6u6SaHxXCti5LPMNeeQSEBSeSLU7oJIQkALs3mVw1ArJGjQHCI6SEaeKQ OlLYUQHHjvKJSfzTmfRABhzSJQZokTkwJa1rfvG1uM13DaFI3p95Ggq/uDDCtixV QOuLGinCRpX/DstTmwRsoH0UGMnrrg7rR37Lb4a5UvCVUbH+I/3kOFjFKD65Je5Z wqsxjBei5SvEjS3W8Mxhd2SAMHaM5xtYol3m83JTb6EV853PyVw3fB3IntVoyqOz Lr2aQtDvVQ/2lBTc+nHAgVhcmGUA3/HjV4zK6o/zF1gGnDoEI0LlbnmZF2MuTtzQ bc7NrCKT3HR63Ul5YTGJsYGpx+VF5G44dRPRMQ4szaJI1X/W0LV7BRkOUM+VEasx AB7Yx2Qf+ITVDPmd5hzGH8QFM2IkMHWcgoeLsDRShGK6n0weLEc= =W4h1 -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Maxime Ripard: Our usual bunch of changes for the next merge window. The most significant addition is the support of the H6 clock unit. Other than that, there's a bunch of fixes for the video clocks on the H3 and H5, and some Kconfig cleanup. * tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name	2018-03-23 09:35:40 -07:00
Lin Huang	9dc486fdf6	clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-03-23 09:09:19 +01:00
Shawn Lin	0d92d1802c	clk: rockchip: Fix error return in phase clock registration The newly added clock notifier may return an error code but so far the error output in the function would only return an error pointer from registering the clock. So when the clock notifier fails the clock would be unregistered but the return would still be the clock pointer which could then not be dereferenced correctly. So fix the error handling to prevent that. Fixes: `60cf09e45f` ("clk: rockchip: Restore the clock phase after the rate was changed") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-03-23 09:08:43 +01:00
Shawn Lin	570fda972b	clk: rockchip: Correct the behaviour of restoring cached phase We can't restore every phase, for instance the invalid phase and the phase for coming rate which is out of the scope of boards' ability. And this patch also corrects the error path to return invalid pointer to clk if clk_notifier_register failed introduced by the same offending commit. Fixes: `60cf09e45f` ("clk: rockchip: Restore the clock phase after the rate was changed") Reported-by: wlq <wlq@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: wlq <wlq@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-03-23 09:02:58 +01:00
Shawn Lin	ce84eca927	clk: rockchip: Fix wrong parents for MMC phase clock for rk3328 commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches some gremlins for clk-rk3328.c that the parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not sclk_{sdmmc, sdio, emmc}. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-03-23 08:58:19 +01:00
Shawn Lin	4b0556a441	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228 commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches one gremlin again for clk-rk3228.c that the parent of SDMMC phase clock should be sclk_sdmmc0, but not sclk_sdmmc. However, the naming of the sdmmc clocks varies in the manual with the card clock having the 0 while the hclk is named without appended 0. So standardize one one format to prevent confusion, as there also is only one (non-sdio) mmc controller on the soc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-03-23 08:49:35 +01:00
Magnus Damm	472f5f3918	clk: renesas: cpg-mssr: Adjust r8a77980 ifdef Adjust the R8A77980-specific #ifdefs to use CLK instead of ARCH to follow same style as other SoCs. Fixes: `ce15783c51` ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2018-03-21 17:35:02 +01:00
Geert Uytterhoeven	2b935d524d	clk: renesas: rcar-gen3: Always use readl()/writel() The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit `30ad3cf00e` ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:35:00 +01:00
Geert Uytterhoeven	f046d6a6bf	clk: renesas: sh73a0: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:58 +01:00
Geert Uytterhoeven	fcf371b351	clk: renesas: rza1: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:57 +01:00
Geert Uytterhoeven	6c669e504a	clk: renesas: rcar-gen2: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:54 +01:00
Geert Uytterhoeven	f32b0696ea	clk: renesas: r8a7740: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:53 +01:00
Geert Uytterhoeven	b86b493eb2	clk: renesas: r8a73a4: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:51 +01:00
Geert Uytterhoeven	8027519840	clk: renesas: mstp: Always use readl()/writel() On arm32, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:49 +01:00
Geert Uytterhoeven	c733c7d937	clk: renesas: div6: Always use readl()/writel() On arm32/arm64, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>	2018-03-21 17:34:29 +01:00
Icenowy Zheng	f422fa558a	clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>	2018-03-21 12:27:13 +01:00
Wei Yongjun	c744b63b6c	clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Fixes: `322269163a` ("clk: hisilicon: add hisi_clk_alloc function.") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:23:41 -07:00
David Lechner	58e1e2d2cd	clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes place during the clk_enable() callback. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	1e88a8d64f	clk: davinci: New driver for TI DA8XX CFGCHIP clocks This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	0c92c71770	dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks This adds a new binding for the clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	aad739f946	clk: davinci: Add platform information for TI DM646x PSC This adds platform-specific declarations for the PSC clocks on TI DM646x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	f41e527575	clk: davinci: Add platform information for TI DM644x PSC This adds platform-specific declarations for the PSC clocks on TI DM644x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	9ab1102cce	clk: davinci: Add platform information for TI DM365 PSC This adds platform-specific declarations for the PSC clocks on TI DM365 based systems. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	b99bfca56e	clk: davinci: Add platform information for TI DM355 PSC This adds platform-specific declarations for the PSC clocks on TI DM355 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	a47d604062	clk: davinci: Add platform information for TI DA850 PSC This adds platform-specific declarations for the PSC clocks on TI DA850/ OMAP-L138/AM18XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	c2952e271b	clk: davinci: Add platform information for TI DA830 PSC This adds platform-specific declarations for the PSC clocks on TI DA830/ OMAP-L137/AM17XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	c6ed4d734b	clk: davinci: New driver for davinci PSC clocks This adds a new driver for mach-davinci PSC clocks. This is porting the code from arch/arm/mach-davinci/psc.c to the common clock framework and is converting it to use regmap to simplify the code. Additionally, it adds device tree support for these clocks. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the keystone driver makes the assumption that there is only one PSC per SoC and uses global variables, but here we have two controllers per SoC. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	21cdf7269f	dt-bindings: clock: New bindings for TI Davinci PSC This adds a new binding for the Power Sleep Controller (PSC) for the mach-davinci family of processors. Note: Although TI Keystone has a very similar PSC, we are not using the existing bindings. Keystone is using a legacy one-node-per-clock binding (actually two nodes if you count the separate reset binding for the same IP block). Also, some davinci LPSCs have quirks that aren't handled by the keystone bindings, so we would be adding one compatible string per clock with quirks instead of just a new compatible string for each controller. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	6ef35851a0	clk: davinci: Add platform information for TI DM646x PLL This adds platform-specific declarations for the PLL clocks on TI DM646x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	d67c13eaf7	clk: davinci: Add platform information for TI DM644x PLL This adds platform-specific declarations for the PLL clocks on TI DM644x based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	650bba61fc	clk: davinci: Add platform information for TI DM365 PLL This adds platform-specific declarations for the PLL clocks on TI DM365 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	dcdd19b269	clk: davinci: Add platform information for TI DM355 PLL This adds platform-specific declarations for the PLL clocks on TI DM355 based systems. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	55b3caed2b	clk: davinci: Add platform information for TI DA850 PLL This adds platform-specific declarations for the PLL clocks on TI DA850/ OMAP-L138/AM18XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00
David Lechner	c92765fdb8	clk: davinci: Add platform information for TI DA830 PLL This adds platform-specific declarations for the PLL clocks on TI DA830/ OMAP-L137/AM17XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-20 10:16:26 -07:00

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